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THURSDAY 7 MARCH, 2002
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| 8A
HOT TOPIC - UML: Using the Unified Modeling Language for Embedded
System Specification
Room A
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Moderator/
Organiser:
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L Lavagno, Politecnico di Torino, IT
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The UML is emerging as a promising standard to flexibly capture
a broad range of requirements for electronic systems. Its
graphical notations allow one to describe semi-formally the
intended behaviour of a system and constraints on its implementation.
Although tool support to computer-aided refinement of such
specifications is still lagging, there are promising proposals
to make it a viable option also for hardware and software
implementations. This tutorial will cover various aspects
of how the UML can be used for both specification and implementation
of embedded electronic systems.
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0900
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THE REAL-TIME UML STANDARD: DEFINITION AND APPLICATION
B Selic, Rational Inc, US
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0930
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UML FOR EMBEDDED SYSTEMS SPECIFICATION AND DESIGN: MOTIVATION
AND OVERVIEW
G Martin, Cadence Design Systems, US
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1000
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A UML-BASED DESIGN METHODOLOGY FOR REAL-TIME AND EMBEDDED
SYTEMS
G de Jong, Telelogic Inc, BE
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1030
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BREAK
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Real-Time Embedded Systems
Room B
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Moderators:
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Z Peng, Linkoping U, SE
J Sifakis, VERIMAG, FR
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The session deals with modelling and analysis of embedded
real-time systems. The first two papers address the issue
of voltage scheduling. The third paper deals with generating
property preserving abstractions of synchronous real-time
programs.
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0900
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AN OPTIMAL VOLTAGE SCHEDULE FOR REAL-TIME SYSTEMS ON A VARIABLE
VOLTAGE PROCESSOR
G Quan and X Hu, Notre Dame U, US
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0930
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A DYNAMIC VOLTAGE SCALING ALGORITHM FOR DYNAMIC-PRIORITY
HARD REAL-TIME SYSTEMS USING SLACK TIME ANALYSIS
W Kim, J Kim and S L Min, Seoul National U, KR
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1000
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EXTENDING SYNCHRONOUS LANGUAGES FOR GENERATING ABSTRACT REAL-TIME
MODELS
G Logothetis and K Schneider, Karlsruhe U, DE
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1030
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POSTERS
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8B - 1
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A NEW TIME MODEL FOR THE SPECIFICATION, DESIGN, VALIDATION
AND SYNTHESIS OF EMBEDDED REAL-TIME SYSTEMS
R Muenzenberger, M Doerfel, F Slomka and R Hofmann, Erlangen
U, DE
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8B - 2
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IMPROVED CONSTRAINTS FOR MULTIPROCESSOR SYSTEM SCHEDULING
M Grajcar and W Grass, Passau U, DE
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1035
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BREAK
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| 8C
Interconnect Modelling
Room C
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Moderators:
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J Phillips, Cadence Berkeley Labs, US
L M Silveira, IST/INESC, PT
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This session presents recent work in the modelling of interconnect
and crosstalk. The first paper presents a methodology for
introducing transmission lines into an analogue mixed-signal
flow. The second paper introduces metrics for capacitive
coupling crosstalk noise. The third and fourth papers discuss
computing dominant poles for reduced order admittance matrices
and library compatible capacitance models for gate-level timing
verification.
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0900
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AN INTERCONNECT-AWARE METHODOLOGY FOR ANALOG AND MIXED SIGNAL
DESIGN, BASED ON HIGH BANDWIDTH (OVER 40 GHz) ON-CHIP TRANSMISSION
LINE APPROACH
D Goren, M Zelikson, T C Galambos, R Gordin, B Livshitz,
A Amir, A Sherman and I A Wagner, IBM, ISR
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0930
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CLOSED-FORM CROSSTALK NOISE METRICS FOR PHYSICAL DESIGN APPLICATIONS
L H Chen, Avant! Corp, US
M Marek-Sadowska, UC Santa Barbara, US
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1000 (S)
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FORMULATION OF LOW-ORDER DOMINANT POLES FOR Y-MATRIX OF INTERCONNECTS
Q Xu and P Mazumder, Michigan U, US
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1015 (S)
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LIBRARY COMPATIBLE Ceff FOR GATE-LEVEL TIMING
B Sheehan, Mentor Graphics, US
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1030
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POSTERS
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8C - 1
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ON-CHIP INDUCTANCE MODELS: 3D OR NOT 3D?
T Lin, M W Beattie and L T Pileggi, Carnegie Mellon U, US
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8C - 2
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IMPROVING THE ACCURACY OF POWER GRID SIMULATION
S R Nassif, IBM, US
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1035
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BREAK
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8D On-Line Testing and Fault Tolerance
Room D
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Moderators:
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L Bouzaida, STMicroelectronics, FR
A D Singh. Auburn U, US
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On-line detection of power supply noise, dependability improvement
insertion at RT level, concurrent error detection exploiting
idle cycles, and fault injection approaches are covered in
this session.
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0900
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SELF-CHECKING SCHEME FOR THE ON-LINE TESTING OF POWER SUPPLY
NOISE
C Metra L Schiano and B Ricco, DEIS – Bologna U, IT
M Favalli, DI – Ferrara U, IT
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0930
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AUTOMATIC MODIFICATIONS OF HIGH LEVEL VHDL DESCRIPTIONS FOR
FAULT DETECTION OR TOLERANCE
R Leveugle, TIMA, Grenoble, FR
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1000 (S)
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EXPLOITING IDLE CYCLES FOR ALGORITHM LEVEL RE-COMPUTING
K Wu and R Karri, Brooklyn Polytechnic U, US
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1015 (S)
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NEW TECHNIQUES FOR SPEEDING-UP FAULT-INJECTION CAMPAIGNS
L Berrojo and I Gónzalez, Alcatel Espacio, ES
F Corno, M Sonza Reorda and G Squillero, Politecnico di Torino,
IT
L Entrena and C López, Carlos III de Madrid U, ES
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1030
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POSTERS
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8D - 1
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A FAST JOHNSON-MOBIUS ENCODING SCHEME FOR FAULT SECURE BINARY
COUNTERS
K S Papadomanolakis, A P Kakarountas, N Sklavos and C E Goutis,
Patras U, GR
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8D - 2
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A NOVEL METHODOLOGY FOR THE CONCURRENT TEST OF PARTIAL AND
DYNAMICALLY RECONFIGURABLE SRAM-BASED FPGAs
M G Gericota and G R Alves, ISEP, PT
M L Silva and J M Ferreira, FEUP/INESC, PT
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8D - 3
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EFFICIENT ON-LINE TESTING METHOD FOR A FLOATING-POINT ITERATIVE
ARRAY DIVIDER
A Drozd, M Lobachev and J Drozd, Odessa State Polytechnic
U, UKR
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1035
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BREAK
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8E Design Space Evaluation
Room E
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Moderators:
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J Teich, Paderborn U, DE
W Kruijtzer, Philips Research, NL
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This session is devoted to the analysis of high-level trade-offs
in system level design. The first paper discusses an abstract
model for exploring different mappings from function to architecture.
The second paper describes techniques for high-level area
and delay estimation for FPGA implementations from matlab
sources. The last two papers examine issues in design space
exploration and simulation performance optimisation in C/C++
-based design environments.
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0900
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SYSTEM DESIGN FOR FLEXIBILITY
C Haubelt and J Teich, Paderborn U, DE
K Richter, TU Braunschweig, DE
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0930
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ACCURATE AREA AND DELAY ESTIMATORS FOR FPGAs
A Nayak, M Haldar, A Choudhary and P Banerjee, Northwestern
U, US
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1000 (S)
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A POWERFUL SYSTEM DESIGN METHODOLOGY COMBINING OCAPI AND
HANDEL-C FOR CONCEPT ENGINEERING
K Buchenrieder, A Pyttel and A Sedlmeier, Infineon Technologies,
DE
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1015 (S)
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AUTOMATED CONCURRENCY RE-ASSIGNMENT IN HIGH LEVEL SYSTEM
MODELS FOR EFFICIENT SYSTEM-LEVEL SIMULATION
N Savoiu, S Shukla and R Gupta, UC Irvine, US
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1030
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POSTER
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8E - 1
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TOP-DOWN SYSTEM LEVEL DESIGN METHODOLOGY USING SpecC, VCC
AND SystemC
L Cai and D Gajski, UC Irvine, US
P Kritzinger and M Olivarez, Motorola, US
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1035
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BREAK
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8F System Design Case Studies (Designers’ Forum)
Room F
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Moderator:
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M Engels, IMEC, BE
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This session presents different real case system design implementations.
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0900 (S)
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HW/SW INTERFACES DESIGN OF A VDSL MODEM USING AUTOMATIC REFINEMENT
OF A VIRTUAL ARCHITECTURE SPECIFICATION INTO A MULTIPROCESSOR
SoC: A CASE STUDY
W Cesario, Y Paviot, A Baghdadi, L Gauthier, D Lyonnard,
G Nicolescu, S Yoo and A A Jerraya, TIMA, Grenoble, FR
M Diaz Nava, STMicroelectronics, FR
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0915 (S)
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DEVELOPMENT OF A SINGLE CHIP SPEECH RECOGNITION SYSTEM USING
A HW/SW CODESIGN METHODOLOGY
S Bocchio, A Rosti, M Borgatti, L Cali’, M Besana and F Lertora,
STMicroelectronics, IT
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0930 (S)
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A DUAL-PROCESSOR SYSTEM-ON-CHIP FOR ELECTRONICS CARTHOGRAPHIC
APPLICATIONS: A DESIGN CASE STUDY
L Fanucci, CSMDR, IT
L Bertini, Pisa U, IT
M De Marinis, Pisa Research Consortium, IT
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0945 (S)
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SATELLITE TUNER SINGLE CHIP SIMULATION WITH ADVANCED DESIGN
SYSTEM
P Busson, A Moutard, B Louis-Gavet, P Dautriche, F Lemery,
C Pujol and J-P Morin, STMicroelectronics, FR
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1000 (S)
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FAST ETHERNET MEDIA ACCESS CONTROLLER CORE
G Paya, M Martinez-Peiro, F J Ballester, R Gadea and V Herrero,
UP Valencia, ES
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1015 (S)
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VIRTUAL SoC PROTOTYPING: CASE STUDY FOR A TRANSACTIONAL
MODEL OF AN USB DRIVER
V Amadio, M Caldari, M Conti, E Corinti, P Crippa, S Orcioni
and C Turchetti, Ancona U, IT
M Coppola, STMicroelectronics, FR
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1030
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BREAK
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9A HOT TOPIC – From System Specification to Layout:
Seamless Top-Down Design Methods for Analogue and Mixed Signal
Applications
Room A
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Moderators/
Organisers:
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I Rugen-Herzig, Infineon Technolgies, DE
R Sommer, Infineon Technologies, DE
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The session is dedicated to latest R&D activities within
the MEDEA+ project ANASTASIA+. Main focus will be the development
of seamless top-down design methods for integrated analogue
and mixed-signal systems and to achieve a high level of automation
and reuse in the A/MS design process. These efforts are motivated
by the urgent need to close the current gap in the industrial
design flow between system specification and design on the
one hand and block-level circuit design on the other hand.
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1100
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TOP-DOWN DESIGN FLOW – APPLICATIONS FROM CIRCUIT SIZING,
DESIGN CENTERING, AND AUTOMATED BEHAVIORAL MODELING
R Sommer, M Thole and E Hennig, Infineon Technologies, DE
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1130
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MODELING AND SIMULATION OF SPECIFIC FUNCTIONALITIES – SIGMA-DELTA
U Gatti, Siemens ICN, IT
P Malcovati, Pavia U, IT
F Maloberti, Texas A&M U, US
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1200
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MIXED-SIGNAL SYSTEM ON CHIP DESIGN ENVIRONMENT
C Einwich, C Clauss and P Schwarz, FhG IIS/EAS Dresden, DE
G Noessing, Infineon Technologies, AT
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1230
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LUNCH
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9B Architectural Level Synthesis
Room B
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Moderators:
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P Eles, Linkoping U, SE
B Mesman, Philips/TU Eindhoven, NL
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This session presents new research on design exploration,
at the architectural level, oriented to the synthesis of application
specific memory systems and datapaths.
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1100
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MEMORY SYSTEM CONNECTIVITY EXPLORATION
P Grun, N Dutt and A Nicolau, UC Irvine, US
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1130
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PERFORMANCE-AREA TRADE-OFF ADDRESS GENERATORS FOR ADDRESS
DECODER-DECOUPLED MEMORY
S Hettiaratchi, P Y K Cheung and T J W Clarke, Imperial College,
UK
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1200
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MULTIPLE-PRECISION CIRCUITS ALLOCATION INDEPENDENT OF DATA-OBJECTS
LENGTH
M C Molina, J M Mendias and R Hermida, Madrid Complutense
U, ES
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1230
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POSTERS
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9B - 1
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COMPILE-TIME AREA ESTIMATION FOR FPGA-BASED RECONFIGURABLE
SYSTEMS
D Kulkarni and W A Najjar, UC Riverside, US
R Rinker, Idaho U, US
F J Kurdahi, UC Irvine, US
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9B - 2
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MAXIMIZING CONDITONAL REUSE BY PRE-SYNTHESIS TRANSFORMATIONS
O Penalba, J M Mendias and R Hermida, Madrid Complutense
U, ES
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9B - 3
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CONTROL CIRCUIT TEMPLATES FOR ASYNCHRONOUS BUNDLED-DATA PIPELINES
S Tugsinavisut and P A Beerel, Southern California U, US
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1235
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LUNCH
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9C Advanced Linear Modelling Techniques
Room C
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Moderators:
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P Feldmann, Celight Inc, US
G Vandersteen, IMEC, BE
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This session brings together a number of papers on system
modelling. The first paper addresses the problem of time-varying
linear system modelling. It introduces an efficient Krylov
subspace based reduction which uses time-domain integration
for linear operator evaluation. The second paper presents
a technique to generate passive rational models for systems
characterised in the frequency domain. The last paper describes
a model reduction technique which approximates the time domain
response using Laguerre polynomials.
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1100
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EFFICIENT MODEL REDUCTION OF LINEAR TIME-VARYING SYSTEMS
VIA COMPRESSED TRANSIENT SYSTEM FUNCTION
E Gad and M Nakhla, Carleton U, CA
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1130
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PASSIVE CONSTRAINED RATIONAL APPROXIMATION ALGORITHM USING
NEVANLINNA-PICK INTERPOLATION
C P Coelho and L M Silveira, IST/INESC/Cadence European Laboratories,
PT
J R Phillips, IST/TU Lisbon, PT
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1200
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MODEL REDUCTION IN THE TIME-DOMAIN USING LAGUERRE POLYNOMIALS
AND KRYLOV METHODS
Y Chen, V Balakrishnan, C-K Koh and K Roy, Purdue U, US
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1230
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POSTERS
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9C - 1
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SIMPLE AND EFFICIENT APPROACH FOR SHUNT ADMITTANCE PARAMETERS
CALCULATIONS OF VLSI ON-CHIP INTERCONNECTS ON SEMICONDUCTING
SUBSTRATE
H Ymeri, B Nauwelaers and S Vandenberghe, KU Leuven, BE
K Maex, D De Roest and M Stucchi, IMEC, BE
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9C - 2
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COMPACT MACROMODEL FOR LOSSY COUPLED TRANSMISSION LINES
R Khazaka and M Nakhla, Carleton U, CA
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9C - 3
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A STANDARD MODEL FOR PREDICTING THE PARASITIC
S Baffreau and E Sicard, INSA, FR
S Calvet, Motorola, FR
C Huet, Airbus, FR
C Marot, Siemens, FR
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9C - 4
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EMC DESIGN METHOD OF HIGH-DENSITY INTEGRATED CIRCUITS
J-L Levant, Atmel, FR
M Ramdani, ESEO, FR
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1235
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LUNCH
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9D Memory Testing and ATPG Issues
Room D
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Moderators:
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H Obermeir, Infineon Technologies, DE
M Sonza Reorda, Politecnico di Torino, IT
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The first two papers introduce new test techniques for memories;
the following two address the issues of untestable fault identification
and test oriented modelling.
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1100
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AN OPTIMAL ALGORITHM FOR THE AUTOMATIC GENERATION OF MARCH
TESTS
A Benso, S Di Carlo, G Di Natale and P Prinetto, Politecnico
di Torino, IT
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1130 (S)
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MINIMAL TEST FOR DETECTING STATE COUPLING FAULTS IN MEMORIES
A J van de Goor, TU Delft, NL
M S Abadir and A Carlin, Motorola, US
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1145 (S)
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MAXIMIZING IMPOSSIBILITIES FOR UNTESTABLE FAULT IDENTIFICATION
M S Hsiao, Virginia Tech, US
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1200
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AUTOMATED MODELING OF CUSTOM DIGITAL CIRCUITS FOR TEST
S Bose, Intel Corporation, US
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1230
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LUNCH
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9E Embedded Software Performance Analysis and Optimisation
Room E
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Moderators:
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H Hsieh, UC Riverside, US
R Lauwereins, IMEC, BE
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This session deals with the important issue of software development
for embedded systems. The session will start with a discussion
of scheduling, and identifying false path in scheduling analysis.
Next, the related issue of performance estimation is presented.
Lastly, the session closes with two short papers on cache
optimisation.
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1100
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FALSE PATH ELIMINATION IN QUASI-STATIC SCHEDULING
G Arrigoni, L Duchini and C Passerone, Politecnico di Torino,
IT
L Lavagno, Politecnico di Torino, IT
Y Watanabe, Cadence Design Systems, US
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1130
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A DATA ANALYSIS METHOD FOR SOFTWARE PERFORMANCE PREDICTION
G Bontempi, IMEC, BE
W Kruijtzer, Philips Research, NL
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1200 (S)
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A CODE TRANSFORMATION-BASED METHODOLOGY FOR IMPROVING I-CACHE
PERFORMANCE OF MULTIMEDIA APPLICATIONS
N Liveris, Northwestern U, US
N D Zervas, ALMA Technologies, GR
D Soudris , Thrace Democritus U, GR
C E Goutis, Patras U, GR
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1215 (S)
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A COMPILER-BASED APPROACH FOR IMPROVING INTRA-ITERATION DATA
REUSE
M T Kandemir, Pennsylvania State U, US
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1230
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POSTERS
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9E - 1
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AUTOMATIC TOPOLOGY-BASED IDENTIFICATION OF INSTRUCTION-SET
EXTENSIONS FOR EMBEDDED PROCESSORS
L Pozzi, M Vuletic and P Ienne, EPFL, CH
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9E - 2
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TUNING PLATFORMS WITH CONFIGURABLE VOLTAGE AND CACHE
T Givargis, UC Irvine, US
F Vahid and J Villarreal, UC Riverside, US
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1235
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LUNCH
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9F Testing and Design for Testability Methodologies
(Designers’ Forum)
Room F
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Moderator:
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F Fummi, Verona U, IT
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This session highlights the application of design for testability
techniques to real designs and problems related to designing
testable and fault tolerant actual systems.
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1100 (S)
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CONSTRAINED LOGIC BIST FOR MICROPROCESSORS
S Kundu, S Sengupta, D Goswami and R Galivanche, Intel Corporation,
US
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1115 (S)
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A BIST: TESTING EXTERNAL MEMORIES AND THEIR INTERCONNECTS
H Kim, X Gu and S Chung, Cisco Systems, US
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1130 (S)
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A LOW-OVERHEAD SCAN-BASED BIST TECHNIQUE BASED ON DATA REINSTATE
METHOD TO TEST EMBEDDED SRAMs IN MAJC MICROPROCESSOR
R Pendurkar, Sun Microsystems, US
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1145 (S)
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MULTI-PORT G.shdsl DFT FEATURES
C M Bui, Centillium Communications, US
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1200 (S)
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DESIGNING A LOW POWER FAULT-TOLERANT MICROCONTROLLER FOR
MEDICINE INFUSION DEVICES
A P Kakarountas, K S Papadomanolakis, V Spiliotopoulos and
C E Goutis, Patras U, GR
S Nikolaidis, Thesalloniki U, GR
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1215 (S)
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HIGH-RESOLUTION TIMING MEASUREMENT SYSTEM
B M Rogina, Rudjer Boskovic Institute, CR
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1230
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LUNCH
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9G TECHNICAL PLENARY – 40 Years of EDA
Room G
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1345 – 1430
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Moderator: A Jerraya, TIMA, Grenoble, FR
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EUROPEAN CAD FROM THE 60’S TO THE NEW MILLENIUM
Joseph Borel, J.B.-R&D Consulting, FR
CAD has always been hardly understood by the CEO’s of companies
because it obeys rules (if any) very different from the process.
A rich variety of CAD and TCAD solutions have been developed
in Europe in the early days of the CAD industry. These solutions
have come to introduce real innovations in the field, but
because they were mostly internal to the companies they have
never reached the proper engineering level that would have
enabled their introduction in the market. A review of the
CAD history activity in Europe will be presented in this Plenary
Session, together with some prospects on how it could evolve
in the coming years and change from its lackluster industrial
visibility
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10A HOT TOPIC – Design Technology for Networked
Reconfigurable FPGA Platforms
Room A
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Organiser/
Moderator:
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I Bolsens, Xilinx, US
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Speakers:
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D Verkest, IMEC, BE
S Guccione, Xilinx, US
S Singh, Xilinx, US
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1430-1600
Internet has become a driving force for the deployment of
embedded systems. Software embedded systems often do not
offer the best solution in terms of cost, speed and power.
It will be demonstrated in this session that FPGA platforms
create a good compromise between high performance and maintaining
the capability of networked reconfiguration. During the first
part of the presentation we will discuss a user scenario of
networked reconfigurable hardware. An appliance equipped
with a reconfigurable FPGA platform localises a reconfiguration
server.
This session will explain the future capabilities of the
above methodology and the requirements wrt future design technology.
We will highlight the need of higher level design methods
and tools in order to make the transparent mapping of an application
onto a mixed hardware/software platform possible as well as
the need for high speed dynamic reconfiguration on multiple
FPGA platforms.
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1600
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CLOSE
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10B High-Level Synthesis and Asynchronous Pipelines
Room B
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Moderators:
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N Dutt, UC Irvine, US
M Renaudin, TIMA, Grenoble, FR
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The first two papers present new templates to build fine-grain
high-speed asynchronous pipelines using different approaches
for completion detection. The next two papers address low-power
and instruction set synthesis.
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1430
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HIGH-SPEED NON-LINEAR ASYNCHRONOUS PIPELINES
R O Ozdag and P A Beerel, Southern California U, US
M Singh, UNC, US
S M Nowick, Columbia U, US
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1500 (S)
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SINGLE-TRACK ASYNCHRONOUS PIPELINE TEMPLATES USING 1-OF-N
ENCODING
M Ferretti and P A Beerel, Southern California U, US
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1515 (S)
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POWER-MANAGEABLE SCHEDULING TECHNIQUE FOR CONTROL DOMINATED
HIGH-LEVEL SYNTHESIS
C Chen, Windsor U, CA
M Sarrafzadeh, UC Los Angeles, US
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1530 (S)
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PRACTICAL INSTRUCTION SET AND COMPILER DESIGN USING STATIC
RESOURCE MODEL
Q Zhao, TU Eindhoven, NL
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1545
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CLOSE
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10C Coupling and Switching Noise Modelling within
Integrated Circuits
Room C
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Moderators:
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E Sicard, INSA, FR
G Vandenbosch, KU Leuven, BE
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This session deals with parasitic coupling effect and switching
noise analysis within integrated circuits. Concerning coupling
analysis, a hierarchical substrate coupling tool is proposed
for interference reduction, and a fast method for coupling
simulation within microwave circuits is presented. Secondly,
an accurate estimation technique is proposed for switching
noise analysis, and a macro modelling approach for i/o switching
is presented, for signal integrity simulation.
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1430
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HIERARCHICAL SIMULATION OF SUBSTRATE COUPLING IN MIXED-SIGNAL
ICs CONSIDERING THE POWER SUPPLY NETWORK
T Brandtner, Infineon Technologies, AT
R Weigel, Linz U, AT
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1500
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FAST METHOD TO INCLUDE PARASITIC COUPLING IN CIRCUIT SIMULATIONS
B L A Van Thielen and G A E Vandenbosch, KU Leuven, BE
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1530 (S)
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ACCURATE ESTIMATING SIMULTANEOUS SWITCHING NOISES BY USING
APPLICATION SPECIFIC DEVICE MODELING
L Ding and P Mazumder, Michigan U, US
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1545 (S)
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MACROMODELING OF DIGITAL I/O PORTS FOR SYSTEM EMC ASSESSMENT
I S Stievano, F G Canavero and I A Maio, Politecnico di Torino,
IT
Z Chen, B Becker and G Katopis, IBM, US
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1600
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CLOSE
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10D PANEL – Formal Verification Techniques: Industrial
Status and Perspectives
Room D
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1430-1600
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Organiser:
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I Moussa, TNI-Valiosys, FR
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Moderator:
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R Pacalet, ENST Paris, FR
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Panellists:
|
J Blasquez, Texas Instruments, Villeneuve-Loubet, FR
M van Hulst, Philips, Eindhoven, NL
A Fedeli, STMicroelectronics, Agrate, IT
J-L Lambert, TNI-Valiosys, FR
D Borrione, TIMA-UJF, FR
C Hanuch, Verisity, FR
P Bricaud, Mentor Graphics, FR
S Meier, Synopsys, US
|
|
Design verification presents the biggest bottleneck in digital
hardware design. Major hardware bugs found in ASIC design
may cause expensive project delays when they are discovered
during system test on the real silicon chip. The consequences
are severe, from cost over-runs to lost market opportunity.
Simulation and emulation tools, which are traditionally used
to find bugs in a design, often cannot find the corner cases
or hard-to-find bugs that may occur only after hundreds of
thousands of cycles, and are well beyond the reach of conventional
simulation and emulation technologies. Formal methods have
emerged as an alternative approach to ensure the quality and
correctness of hardware designs, overcoming some of the limitations
of traditional validation techniques such as simulation and
testing.
1630 CLOSE
|
| |
|
10E Power Optimisation for Embedded Processors
Room E
|
|
Moderators:
|
W Fornaciari, Politecnico di Milano, IT
L Lavagno, Politecnico di Torino, IT
|
|
The focus of this session is on the most important aspects
impacting the power budget of embedded processors. The session
will address the analysis of operation complexity, procedure
inlining, bus and cache encoding/timing.
|
|
1430
|
LOW POWER EMBEDDED SOFTWARE OPTIMIZATION USING SYMBOLIC ALGEBRA
A Peymandoust, T Simunic and G De Micheli, Stanford U, US
|
|
1500
|
AN ADAPTIVE DICTIONARY ENCODING SCHEME FOR SoC DATA BUSES
T Lv and W Wolf, Princeton U, US
J Henkel and H Lekatsas, NEC, US
|
|
1530 (S)
|
POWER EFFICIENT EMBEDDED PROCESSOR IP’s THROUGH APPLICATION-SPECIFIC
TAG COMPRESSION IN DATA CACHES
P Petrov and A Orailoglu, UC San Diego, US
|
|
1545 (S)
|
SYSTEMATIC POWER-PERFORMANCE TRADE-OFF IN MPEG-4 BY MEANS
OF SELECTIVE FUNCTION INLINING STEERED BY ADDRESS OPTIMISATION
OPPORTUNITIES
M Palkovic, M Miranda and F Catthoor, IMEC, BE
|
|
1600
|
CLOSE
|
|
|
10F Analogue and Mixed-Signal Design (Designers’
Forum)
Room F
|
|
Moderatos:
|
C Dufaza, LIRMM, FR
|
|
This session will present some design experiences for analogue
circuits sizing and two design methodologies for the analysis
of analogue and mixed-signal circuits.
|
|
1430 (S)
|
DESIGN OF A BROADBAND SD MODULATOR IN 2.5-V CMOS
R del Rio, F Medeiro, J M de la Rosa, B Perez-Verdu and A
Rodriguez-Vazquez, IMSE-CNM, ES
|
|
1445 (S)
|
TECHNOLOGY MIGRATION OF A HIGH-PERFORMANCE CMOS AMPLIFIER
USING AN AUTOMATED FRONT-TO-BACK ANALOG DESIGN FLOW
S Dugalleix and F Lemery, STMicroelectronics, FR
A Shah, Neolinear Inc, US
|
|
1500 (S)
|
AN AUTOMATED APPROACH FOR SIZING COMPLEX ANALOG CIRCUITS
IN A SIMULATION-BASED FLOW
E Hennig and R Sommer, Infineon Technologies, DE
L Charlack, Neolinear Inc, US
|
|
1515 (S)
|
A FRAMEWORK FOR ANALYSIS OF SUBSTRATE COUPLING METHODS FOR
MIXED-SIGNAL CIRCUITS
J P Amaro, INESC, PT
J R Phillips, Cadence Berkeley Labs, US
L M Silveira, INESC/Cadence European Labs, PT
|
|
1530 (S)
|
SYMBOLIC ANALYSIS IN ANALOG IC DESIGN: A VIEW FROM THE INDUSTRIAL
CAD PERSPECTIVE
E Hennig and R Sommer, Infineon Technologies, DE
|
|
1545 (S)
|
STASTICAL CORNER MODELS FOR ROBUST DESIGN
M Kocher and G Rappitsch, Autriamicrosystems, AT
|
|
1600
|
CLOSE
|
| |
|
PCB SYMPOSIUM
LEVEL 1– ROOM W
|
This year's PCB Symposium is themed "Challenges
to get High-Speed Boards Designed and Manufactured in
Time".
Over the last years IC-designers invented new methodologies
- like IPs and ASSPs - to significantly reduce the development
time. This brought the PCB-designers - being already
the last in the R&D chain - back into the critical
spot to get the product out of the door within the tight
timeframes. But due to drastically increasing clock
frequencies on the boards and intensified EMI requirements
the designer is losing productivity.
As it has been working for years in the Systems-on-Silicon
world, the buzzword"correct by construction"
has to become reality as well in the Systems-on-Board
world.
The leading EDA vendors with the focus on addressing
the PCB design challenges will introduce technically
in-depth papers, presented by their technical specialists.
The presentations will cover the emerging new PCB technologies,
including optical interconnect. Automatic handling routines
are discussed to get a board EMI-compliant. With up
to 90% of the nets on a board being considered critical
for high-speed and signal integrity, ways are shown
how to deal with those interconnects automatically in
order to avoid time consuming prototypes. Since today's
boards are manufactured across the globe on different
processes, the audience will learn about possibilities
to address "design-for-manufacturability"
in a productive way.
Innovation this year: During the panel session
at the end with vendor experts and two designers, the
EDA-Vendor Design-Award will be presented in
3 categories "most challenging high-speed design",
"the most complex board", "the most elegant
design solution". To qualify for this award in
one of the categories, please contact carsten.elgert@mentor.com
no later than Jan 11th, 2002 for details.
The target audience is the PCB- and Systems-designer
who is involved in leading-edge products.
|
| 10:00 |
Modelling, Simulating
and Optimising a Power Distribution System (PDS) in the
Frequency Domain |
| |
Heiko Dudek, Cadence
This paper discusses a new methodology that
addresses challenges in ensuring reliable power delivery
in high-speed PCB designs. It allows engineers and designers
early and better understanding of the power delivery
system (PDS) in high-speed design. In the early 90s,
when designers worked with 5-volt logic and 5 watts
of power that, as a result, pulled 1 amp, designing
the power delivery system was not too difficult. However,
in today's complex microprocessor-based designs logic
swing is down to almost 1 volt, power dissipation increased
to 100 watts, and, as a result, current requirement
can be 100 amps. If the required amount of power cannot
be delivered, system failures, radiated emissions (EMI),
interference between different functional blocks around
the PCB (common impedance coupling) and timing problems
can occur. The new methodology takes the power integrity
challenge and approaches it in pretty much the same
way classic signal integrity issues, like timing budgeting
or waveform integrity are being solved, by addressing
them early in the design cycle. What typically is a
post-layout-verification process can be turned into
an integrated design method by looking at the power
delivery path's impedance in the frequency domain. Now
power stability issues that could cause delay in product
development can be identified and resolved early.
|
| 10:30 |
Changing the
Flow of High-Speed Design |
| |
Mic Farris, Innoveda
High-speed design has become increasingly
critical as board sizes decrease and board complexity,
clock speeds, and edge rates increase. To minimize these
problems, design teams now plan for high-speed issues,
putting much time and effort into the development of
geometric net constraints by using design-oriented signal
integrity tools. However, many of these tools are designed
to apply constraints in the PCB designer's world, working
on an existing PCB database and converting electrical
constraints to geometric ones. While this back-end-focused
design process predominates today, the flow of high-speed
design is changing to allow the electrical engineer
to define electrical constraints early in the design
definition stage. By considering high-speed issues as
early as possible, they can be removed from a design's
critical path.
|
| 11:00 |
Analysis Driven
Auto-routing Options
What are the methods for the engineer to design a physical
system that meets electrical constraints? |
| |
Stephane Rousseau, Mentor
Today's (and tomorrow's) high-speed designs require
specific design practices to ensure signal integrity
concerns are met in the final product. What are the
signal integrity challenges? Should you be concerned
about signal integrity? Will accurate Delay Management
be critical to my design? . When should I be concerned
about Crosstalk? How will Crosstalk affect my design?
Can you get by without simulation? This presentation
will describe these concerns found in today's high-speed
PCBs. The paper will refer to real design problems and
their solutions, and illustrate how to "design-out"
SI problems "up front" rather than later in
the more-expensive & time-consuming parts of the
process.
|
| 11:30 |
The Integration
of PCB Design into PCBA Manufacturing |
| |
Peter Clegg, Valor
While many of today's electronic products, and component
packaging, have seen a dramatic transformation from
bulky, heavy, power hungry, semi-permanent systems to
small, lightweight, power thrifty, user friendly portable
products. However, the process steps used in manufacturing
the products has changed only slightly. Many of these
process steps are still performed using manual or semi-automated
systems to transform design data into production information.
Integration manufacturing requirements directly into
the PCB design process has improved the ability to convert
design data into meaningful manufacturing information.
As PCBA designs increase in complexity, and "Time
to Market" decreases, integrated systematic electronic
tools have evolved to meet this demand.
|
| 12:00 |
Panel Session |
| 12:30 CLOSE |
|
|
| |
|
POSTER
SESSIONS
LEVEL
2 – CONFERENCE ROOM FOYER
Please see below the complete list of Posters which will
be presented during the Conference. All posters will be shown
during the 3 days of the Conference. Authors will be standing
by their posters during the two breaks on Wednesday and at
the break immediately after the session in which the Poster
is presented. Authors will also be able to introduce their
Poster during their sessions, using one summary slide. The
posters will be conveniently located just outside the lecture
theatre in which they are presented. The boards are numbered
with the relevant session number first, i.e. 1B, 5B, 7C and
followed by the Poster’s individual number within that session,
i.e. – 1, - 2, - 3.
|
|
1B – 1
|
AN APPROACH TO MODEL CHECKING FOR NONLINEAR ANALOG SYSTEMS
W Hartong, L Hedrich and E Barke, Hannover U, DE
|
|
2B – 1
|
SPEEDING UP SAT FOR EDA
S Pilarski and G Hu, Synopsys, US
|
|
2B – 2
|
SEARCH-BASED SAT USING ZERO-SUPPRESSED BDDS
F A Aloul, M N Mneimneh and K A Sakallah, Michigan U, US
|
|
3B – 1
|
AN ENCODING TECHNIQUE FOR LOW POWER CMOS IMPLEMENTATIONS
OF CONTROLLERS
M Martinez, M J Avedillo, J M Quintana, M Koegst, S T Ruelke
and H Susse, CNM-IMSE, ES
|
|
3B – 2
|
COMPOSITION TREES IN FINDING BEST VARIABLE ORDERINGS FOR
ROBDDS
E Dubrova, Royal IT, SE
|
|
3B – 3
|
A DIRECT MAPPING SYSTEM FOR DATAPATH MODULE AND FSM IMPLEMENTATION
INTO LUT-BASED FPGAs
J Abke and E Barke, Hannover U, DE
|
|
3B – 4
|
CONCURRENT AND SELECTIVE LOGIC EXTRACTION WITH TIMING CONSIDERATION
P Rezvani and M Pedram, Southern California U, US
|
|
3B – 5
|
IMPROVED TECHNOLOGY MAPPING FOR PAL-BASED DEVICES USING A
NEW APPROACH TO MULTI-OUTPUT BOOLEAN FUNCTIONS
K Dariusz, Silesian UT, PL
|
|
3B – 6
|
EFFICIENT AND EFFECTIVE REDUNDANCY REMOVAL FOR MILLION-GATE
CIRCUITS
M Berkelaar and K van Eijk, Magma Design Automation, NL
|
|
4B – 1
|
VISUALIZATION OF PARTIAL ORDER MODELS IN VLSI DESIGN FLOW
A Bystrov, M Koutny and A Yakovlev, Newcastle upon Tyne U,
UK
|
|
4B – 2
|
HIGH-LEVEL MODELING AND DESIGN OF ASYNCHRONOUS ARBITERS FOR
ON-CHIP COMMUNICATION SYSTEMS
J-B Rigaud, L Fesquet and M Renaudin, TIMA, Grenoble, FR
J Quartana, STMicroelectronics, FR
|
|
5B – 1
|
POWER-EFFICIENT TRACE CACHES
J Hu, N Vijaykrishnan, M Kandemir and M J Irwin, Pennsylvania
State U, US
|
|
5B – 2
|
TIME DOMAIN MODELING OF THE POWER CONSUMPTION OF A 32 BIT
MICROPROCESSOR
G Caldentey, J Cid, J Rius, X Amela, S Manich and R Rodriguez,
Catalunya UP, ES
|
|
5B – 3
|
REDUCING CACHE ACCESS ENERGY IN ARRAY-INTENSIVE APPLICATIONS
M Kandemir, Pennsylvania State U, US
I Kolcu, Manchester U, UK
|
|
6B – 1
|
THE USE OF RUNTIME CONFIGURATION CAPABILITIES FOR NETWORKED
EMBEDDED SYSTEMS
C Nitsch and U Kebschull, Leipzig U, DE
|
|
6B – 2
|
A SAT SOLVER USING SOFTWARE AND RECONFIGURABLE HARDWARE
I Skliarova and A B Ferrari, Aveiro U, PT
|
|
8B – 1
|
A NEW TIME MODEL FOR THE SPECIFICATION, DESIGN, VALIDATION
AND SYNTHESIS OF EMBEDDED REAL-TIME SYSTEMS
R Muenzenberger, M Doerfel, F Slomka and R Hofmann, Erlangen
U, DE
|
|
8B – 2
|
IMPROVED CONSTRAINTS FOR MULTIPROCESSOR SYSTEM SCHEDULING
M Grajcar and W Grass, Passau U, DE
|
|
9B – 1
|
COMPILE-TIME AREA ESTIMATION FOR FPGA-BASED RECONFIGURABLE
SYSTEMS
D Kulkarni and W A Najjar, UC Riverside, US
R Rinker, Idaho U, US
F J Kurdahi, UC Irvine, US
|
|
9B – 2
|
MAXIMIZING CONDITONAL REUSE BY PRE-SYNTHESIS TRANSFORMATIONS
O Penalba, J M Mendias and R Hermida, Madrid Complutense
U, ES
|
|
9B – 3
|
CONTROL CIRCUIT TEMPLATES FOR ASYNCHRONOUS BUNDLED-DATA PIPELINES
S Tugsinavisut and P A Beerel, Southern California U, US
|
|
1C – 1
|
TRANSFORMING ARBITRARY STRUCTURES INTO TOPOLOGICALLY EQUIVALENT
SLICING STRUCTURES
O Peyran and W Zhuang, Singapore Inst. of High Performance
Computing, SING
|
|
1C – 2
|
A NEW FORMULATION FOR SOC FLOORPLAN AREA MINIMIZATION PROBLEM
C-H Lee, Y-C Lin, W-Y Fu, C-C Chang and T-M Hsieh, Chung-Yuan
Christian U, ROC
|
|
1C - 3
|
NON-RECTANGULAR SHAPING AND SIZING OF SOFT MODULES FOR FLOORPLAN
DESIGN IMPROVEMENT
C C N Chu, F Y Young and W S Luk, The Chinese U, HK
|
|
2C – 1
|
EZ ENCODING: A CLASS OF IRREDUNDANT LOW POWER CODES FOR
DATA ADDRESS AND MULTIPLEXED ADDRESS BUSES
Y Aghaghiri and M Pedram, Southern California U, US
F Fallah, Fujitsu Labs of America, US
|
|
2C – 2
|
ESTIMATION OF POWER CONSUMPTION IN ENCODED DATA BUSSES
A Garcia, L D Kabulepa and M Glesner, TU Darmstadt, DE
|
|
3C – 1
|
OPTIMIZATION TECHNIQUES FOR DESIGN OF GENERAL AND FEEDBACK
LINEAR ANALOG AMPLIFIER WITH SYMBOLIC ANALYSIS
T C Hieu and E-H Horneber, TU Braunschweig, DE
|
|
3C – 2
|
CRITICAL COMPARISON AMONG SOME ANALOG FAULT DIAGNOSIS PROCEDURES
BASED ON SYMBOLIC TECHNIQUES
A Luchetta, Basilicata C. da Macchia U, IT
S Manetti and M C Piccirilli, Florence U, IT
|
|
4C – 1
|
THE SELECTIVE PULL-UP (SP) NOISE IMMUNITY SCHEME FOR DYNAMIC
CIRCUITS
M R Stan and A Panigrahi, Virginia U, US
|
|
4C – 2
|
DESIGN AND VALIDATION FLOW INCLUDING SUBSTRATE PARASITIC
EXTRACTION FOR RF CIRCUITS
A Cathelin, D Saias and D Belot, STMicroelectronics, FR
Y Leclercq and F Clement, Simplex Solutions, FR
|
|
4C – 3
|
A COMPLETE PHASE-LOCKED LOOP POWER CONSUMPTION MODEL
D Duarte, V Narayanan and M J Irwin, The Pennsylvania State
U, US
|
|
5C – 1
|
STATISTICAL TIMING DRIVEN PARTITIONING FOR VLSI CIRCUITS
C Ababei and K Bazargan, Minnesota U, US
|
|
6C – 1
|
DAISY-CT: A HIGH-LEVEL SIMULATION TOOL FOR CONTINUOUS-TIME
DS MODULATORS
K Francken, M Vogels, E Martens and G Gielen, KU Leuven,
BE
|
|
6C - 2
|
AUTOMATED OPTIMAL DESIGN OF SWITCHED-CAPACITOR CIRCUITS
A Hassibi and M Hershenson, Barcelona Design, ES
|
|
8C – 1
|
ON-CHIP INDUCTANCE MODELS: 3D OR NOT 3D?
T Lin, M W Beattie and L T Pileggi, Carnegie Mellon U, US
|
|
8C – 2
|
IMPROVING THE ACCURACY OF POWER GRID SIMULATION
S R Nassif, IBM, US
|
|
9C – 1
|
SIMPLE AND EFFICIENT APPROACH FOR SHUNT ADMITTANCE PARAMETERS
CALCULATIONS OF VLSI ON-CHIP INTERCONNECTS ON SEMICONDUCTING
SUBSTRATE
H Ymeri and S Vandenberghe, KU Leuven, BE
K Maex, D De Roest and M Stucchi, IMEC, BE
|
|
9C – 2
|
COMPACT MACROMODEL FOR LOSSY COUPLED TRANSMISSION LINES
R Khazaka and M Nakhla, Carleton U, CA
|
|
9C – 3
|
A STANDARD MODEL FOR PREDICTING THE PARASITIC
S Baffreau and E Sicard, INSA, FR
S Calvet, Motorola, FR
C Huet, Airbus, FR
C Marot, Siemens, FR
|
|
9C – 4
|
EMC DESIGN METHOD OF HIGH-DENSITY INTEGRATED CIRCUITS
J-L Levant, Atmel, FR
M Ramdani, ESEO, FR
|
|
1D – 1
|
FINDING A COMMON FAULT RESPONSE FOR DIAGNOSIS DURING SILICON
DEBUG
I Pomeranz, Purdue U, US
J Rajski, Mentor Graphics, US
S M Reddy, Iowa U, US
|
|
1D –2
|
IDDT TESTING OF EMBEDDED CMOS SRAMs
S A Kumar, R Z Makki and D Binkley, North Carolina U, Charlotte,
US
|
|
1D – 3
|
FAULT DETECTION AND DIAGNOSIS USING WAVELET BASED TRANSIENT
CURRENT ANALYSIS
S Bhunia and K Roy, Purdue U, US
|
|
2D – 1
|
AN EFFICIENT TEST AND DIAGNOSIS SCHEME FOR THE FEEDBACK TYPE
OF ANALOG CIRCUITS WITH MINIMAL ADDED CIRCUITS
J W Lin and C L Lee, National Chiao Tung U, ROC
J-E Chen, Chung Hwa U, ROC
|
|
2D – 2
|
ON THE USE OF AN OSCILLATION-BASED TEST METHODOLOGY FOR CMOS
MICRO-ELECTRO-MECHANICAL SYSTEMS
V Beroulle, Y Bertrand, L Latorre and P Nouet, LIRMM, FR
|
|
4D – 1
|
DIRECTED-BINARY SEARCH IN LOGIC BIST DIAGNOSTICS
R Kapur and T W Williams, Synopsys, US
M R Mercer, Texas A&M U, US
|
|
4D – 2
|
AN EVOLUTIONARY APPROACH TO THE DESIGN OF ON-CHIP PSEUDORANDOM
TEST GENERATORS
M Favalli, DI- Ferrara U, IT
M Dalpasso, DEI – Padova U, IT
|
|
5D – 1
|
FAULT ISOLATION USING TESTS FOR NON-ISOLATED BLOCKS
I Pomeranz, Purdue U, US
Y Zorian, LogicVision, US
|
|
6D – 1
|
A HEURISTIC FOR TEST SCHEDULING AT SYSTEM LEVEL
M L Flottes, J Pouget and B Rouzeyre, LIRMM, FR
|
|
6D – 2
|
FORMULATION OF SoC TESTING SCHEDULING AS A NETWORK TRANSPORTATION
PROBLEM
S Koranne and V Suhas, Philips, NL
|
|
8D – 1
|
A FAST JOHNSON-MOBIUS ENCODING SCHEME FOR FAULT SECURE BINARY
COUNTERS
K S Papadomanolakis, A P Kakarountas, N Sklavos and C E Goutis,
Patras U, GR
|
|
8D – 2
|
A NOVEL METHODOLOGY FOR THE CONCURRENT TEST OF PARTIAL AND
DYNAMICALLY RECONFIGURABLE SRAM-BASED FPGAs
M G Gericota and G R Alves, ISEP, PT
M L Silva and J M Ferreira, FEUP/INESC, PT
|
|
8D – 3
|
EFFICIENT ON-LINE TESTING METHOD FOR A FLOATING-POINT ITERATIVE
ARRAY DIVIDER
A Drozd, M Lobachev and J Drozd, Odessa State Polytechnic
U, UKR
|
|
1E – 1
|
POWER MODELING AND REDUCTION OF VLIW PROCESSORS
W Liao and L He, Wisconsin U, Madison, US
|
|
1E – 2
|
AN INSTRUCTION-LEVEL METHODOLOGY FOR POWER ESTIMATION AND
OPTIMIZATION OF EMBEDDED VLIW CORES
A Bona, M Sami, D Sciuto and V Zaccaria, Politecnico di Milano,
IT
C Silvano, U degli Studi di Milano, IT
R Zafalon, STMicroelectronics
|
|
2E – 1
|
THE FRAUNHOFER KNOWLEDGE NETWORK (FKN) FOR TRAINING IN CRITICAL
DESIGN DISCIPLINES
A Sauer and G Elst, FhG IIS/EAS, DE
L Krahn and W John, FhG IZM, DE
|
|
2E – 2
|
COMPARATIVE ANALYSIS AND APPLICATION OF DATA REPOSITORY INFRASTRUCTURE
FOR COLLABORATION-ENABLED DISTRIBUTED DESIGN ENVIRONMENTS
L S Indrusiak, TU Darmstadt, DE/UFRGS, BRZ
M Glesner, TU Darmstadt, DE
R Reis, UFRGS, BRZ
|
|
3E – 1
|
AREA-EFFICIENT MEMORY FOR SELF-PROFILING MICROPROCESSOR PLATFORMS
S Cotterell, F Vahid and R Lysecky, UC Riverside, US
|
|
3E – 2
|
FlexBench: REUSE OF VERIFICATION IP TO INCREASE PRODUCTIVITY
S Stoehr, M Simmons and J Geishauser, Motorola Munich, DE
|
|
5E – 1
|
MAPPABILITY ESTIMATION OF ARCHITECTURE AND ALGORITHM
J-P Soininen, J Kreku and Y Qu, VTT Electronics, FI
|
|
6E – 1
|
BEHAVIOURAL MODELLING OF OPERATIONAL AMPLIFIER FAULTS USING
VHDL-AMS
P R Wilson, J N Ross, M Zwolinski and A D Brown, Southampton
U, UK
Y Kilic, Philips Semiconductors, UK
|
|
6E – 2
|
A PARALLEL LCC SIMULATION SYSTEM
K Hering, Chemnitz U, DE
|
|
6E – 3
|
ERROR SIMULATION BASED ON THE SystemC DESIGN DESCRIPTION
LANGUAGE
F Bruschi, M Chiamenti, F Ferrandi and D Sciuto, Politecnico
di Milano, IT
|
|
6E – 4
|
TOWARDS A KERNEL LANGUAGE FOR HETEROGENEOUS COMPUTING
D Björklund and J Lilius, Turku Center for Computer Science
(TUCS), FI
|
|
8E – 1
|
TOP-DOWN SYSTEM LEVEL DESIGN METHODOLOGY USING SpecC, VCC
AND SystemC
L Cai and D Gajski, UC Irvine, US
P Kritzinger and M Olivarez, Motorola, US
|
|
9E – 1
|
AUTOMATIC TOPOLOGY-BASED IDENTIFICATION OF INSTRUCTION-SET
EXTENSIONS FOR EMBEDDED PROCESSORS
L Pozzi, M Vuletic and P Ienne, EPFL, CH
|
|
9E – 2
|
TUNING PLATFORMS WITH CONFIGURABLE VOLTAGE AND CACHE
T Givargis, UC Irvine, US
F Vahid and J Villarreal, UC Riverside, US
|
|
3F2 - 1
|
STEADY STATE CALCULATION OF OSCILLATORS USING CONTINUATION
METHODS
H G Brachtendorf, S Lampe and R Laur, Bremen U, DE
R Melville, Agere Systems, US
P Feldmann, Celight Inc, US
|
|
|
|
