Dalton Project
University of California
Dept. of Computer Science
Riverside, CA 92521
dalton@cs.ucr.edu

Synopsys Synthesis for Beginners

  1. Synthesizing Files
    1. Go to directory where you downloaded the latest i8051 files
      • cd nameofdirectory
    2. Create a directory called "work" in your project directory
      • mkdir work
    3. Set the execute permission on the zsyn.all script file
      • chmod 700 zsyn.scr
    4. Synthesize the files using the downloaded script file
      • zsyn.scr (this may take up to an hour)
    5. Comment out line 15 in each of the following gate files
      (i.e. change line 15 from "type UNSIGNED is array(INTEGER range <>) of std_logic;" to "--type UNSIGNED is array(INTEGER range <>) of std_logic;") :
      • i8051_alu_gate.vhd
      • i8051_dec_gate.vhd
      • i8051_ram_gate.vhd
      • i8051_rom_gate.vhd
      • i8051_ctr_gate.vhd
    6. Analyze each of the files, there are two ways to do this:
      • Analyze each file seperatley, remebering to compile the innermost entities first by using the following commands:
        • vhdlan i8051_lib.vhd
        • vhdlan i8051_alu_gate.vhd
        • vhdlan i8051_dec_gate.vhd
        • vhdlan i8051_ram_gate.vhd
        • vhdlan i8051_rom_gate.vhd
        • vhdlan i8051_ctr_gate.vhd
        • vhdlan i8051_all.vhd
        • vhdlan i8051_tsb.vhd
      • OR Analyze all the files by altering the script file provided:
        1. Modify the zsim.scr file by changing:
          • "vhdlan i8051_alu" to "vhdlan i8051_alu_gate"
          • "vhdlan i8051_dec" to "vhdlan i8051_dec_gate"
          • "vhdlan i8051_ram" to "vhdlan i8051_ram_gate"
          • "vhdlan i8051_rom" to "vhdlan i8051_rom_gate"
          • "vhdlan i8051_ctr" to "vhdlan i8051_ctr_gate"
        2. Set the execute permission on the script file:
          • chmod 700 zsim.scr
        3. Execute the script file
          • zsim.scr
  2. Tracing Signals
    Note: The C code you wish to simulate should already be present in the i8051_rom.vhd file before you start the synthesis. If it is not, follow the steps below

    Getting your C code ready to synthesize (i.e. converting your C file to VHDL ROM model)


    Last Updated 11/23/1999

    Published by NewIT Labs
    NEW IT Labs