Gomel Fr.Skaryna State University, Belarus
The Head of Information Computing Center
Associated prof. of the Chair "Mathematical Problems of Control"
Tomsk Polytechnical University, Russia
Cybernetic Centre Insitute
Computer Engineering Department
Dr. Vladimir Salit
Prof.Ing. Jaromir Brzobohaty, CSc
Department of Microelectronics
Faculty of Electrical Engineering
and Computer Science
Technical University of Brno
Udolni 53, 60200 Brno
Tel: +420 5 43167160
Fax: +420 5 43167298
1. To develop package of agreements, intrefaces and software procedures, that provide
a) Remote schematic capture and software/VHDL editing
b) Remote control for software compilation, co-simulation of hardware and software as well as for debugging and simulation result analysis.
This package should provide work with Coware, IEESD-2000 (see below), and for all other IDE with respective possibilities
2. To develop tools that provide remote verification of designed projects
In more detail: Let we have full-functional behavioral model of the device (Intel 8051, for example) as well as ful set of testbenches for it (having the model we easy can develop such testbench set) then user can send us his own model (high level, RT level, or synthesizable VHDL), and we'll prove adequacy of his model. Naturally, from our side all work (to get model, start simulation. compare results, send the answer) will be done automatically.
In addition we can calculate additional interesting information (upper limit frequency or number of logical gates in the project, for example)
3) To develop telecommuted training and testing studying courses on VHDL design and testing.
In short I write our answer below.
We'll give any additional information by request with pleasure.
Now we elaborated
"Integrated Environment for Embedded Systems Development" (IEESD-2000)
- schematic capture for embedded systems (SOC and/or SOB)
- we have powerful library of standard component
- user can do own new elements (with any level of difficulty - CPU as well) with the following steps:
- to do picture (to provide schematic capture)
- to do decomposition of the element with our standard components (to provide simulation and generation of synthesizable VHDL)
- to do simulation model of the element with high level programming language (Delphi, C++ Builder) (to provide simulation)
- to do generation of synthesizable VHDL of the element with high level programming language (Delphi, C++ Builder) (to provide generation of synthesizable VHDL)
- in such a way we can research and debug the system with microprocessors!
We have done simulation models and prove the possibilities for the following microcontrollers: Intel 8051 and AVR
More over, we can research and debug MULTI-microprocessor systems
- Co-Simulation and Co-Debugging in IEESD-2000 provides
- hardware engineers - with modern schematic analysis of simulation results
- software engineers - with modern source software debugging windows
- Software engineers can use any tools for compilation of their programs (as we have means to embedd the compilation tools into IEESD-2000) as well as we can tune our compilation tools to proposed language (it is done already for assemblers and we work now for such possibility for C as well as for all another high level programming language)
- Hardware engineers can generate synthesizable VHDL-description of designed hardware (we prove the possibility in PeakVHDL and MaxPlus)
IEESD-2000 has 2 components (HLCCAD+WInter), that may work independently as well.
HLCCAD - to design and debug hardware (or hardware with software - with shortcutted possibilities for software design)
WInter - to design and debug software (or software with hardware with possibility high level hardware simulation ). In addition a user has possibility to work with WInter through INTERNET.
In both cases (HLCCAD, WInter) simulation is faster, and price is lower (both in comparation with IEESD-2000).
Moreover, user can E-mail automatic service (send empty letter to
Published by NewIT Labs