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Lviv Polytechnic National University

Physical Design Automation, SOC, VLSI, FPGA, PCB, Partitioning, Packaging, placement, routing, topological routing, Large and very large size problem for millions of blocks and elements, Combinatorial optimization, NP-hard problems

:: Contact Person

BAZYLEVYCH, Roman (Dr., Professor)
Full Professor
Lviv Polytechnic National University
http://people.polynet.lviv.ua/bazylevych/
rbaz@polynet.lviv.ua
Telephone: +380-322-765712

:: Collaboration
Project Proposal
Title: Physical Design Automation, SOC, VLSI, FPGA, PCB, Partitioning, Packaging, placement, routing, topological routing, Large and very large size problem for millions of blocks and elements, Combinatorial optimization, NP-hard problems
Type Details: Physical Design Automation, SOC, VLSI, FPGA, PCB, Partitioning, Packaging, Placement, Routing, Topological routing, Large and very large size problem for millions of blocks and elements, Combinatorial optimization, NP-hard problems
FP6-IST
Research Interest: Automation, robotics, control engineering; Computer science; Artificial intelligence; Informatics, systems theory; Systems engineering, computer technology
Expiry Date: 2006-12-14
 

:: Target Partner
Expertise: Physical Design Automation, SOC, VLSI, FPGA, PCB, Partitioning, Packaging, Placement, Routing, Topological routing, Large and very large size problem for millions of blocks and elements, Combinatorial optimization, NP-hard problems
Country: Any Country

:: Organisation Details
Name: Lviv Polytechnic National University
Department: Software Engineering Department
Address: 12
Bandera
Street
Lviv   79013
UKRAINE
Type: Research; Education
Details: Wide area Polytechnic University
Keywords: ; CAD,; SOC,; VLSI,; FPGA,; PCB,; Partitioning,; Packaging,; Placement,; Routing,
RCN: 63791    
Quality Validation Date: 2003-03-14    
Update Date: 2003-03-18    

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