Seamless Hello Michael As you requested, following is your System-Level Verification News Update featuring SeamlessR Co-Verification and Platform ExpressTM, platform-based design. _____ IN THIS MAY ISSUE: Technical Papers and Success Stories Processor Support Package Update Technical Events HW/SW Co-Verification Technical Workshops - New Version 5 Press Coverage _____ ÿA ÿA ÿA Technical Papers and Success Stories >ÿÿ Hughes Network Systems Accelerates Time-to-Market of a Next Generation Satellite Packet Processor ÿ This paper details an effort to verify the downlink channel of a broadband-over-satellite ground terminal. The total size of the ASIC was seven million gates, including six Tensilica Xtensa configurable processor cores. To verify the packet processor, we used the Mentor GraphicsR SeamlessR co-verification environment for hardware/software co-verification and debug, Mentor's ModelSimR logic simulator for hardware simulation, and VerisityR's Specman EliteR testbench automation solution. ÿ To obtain this customer success: http://www.mentor.com/seamless/cust_successes/hughes_css.html >ÿÿ Co-Verification Enhances Time to Market Advantage of Platform FPGAs ÿ The growth in the system-on-a-chip (SOC) market is being fueled by the need to increase performance and reliability while reducing overall system costs. Until recently, ASICs were the primary technology available to designers to integrate multiple processing elements required to build systems on a single device. With the introduction of the latest Platform FPGA programmable devices, a compelling new alternative is now available to designers. However, in order to fully extract the full potential of this powerful platform, newer EDA tools and methodologies are required to maintain designer productivity. ÿ Obtain this paper and others in our technical library at: http://www.mentor.com/soc/tpapers ÿA ÿA ÿA Processor Support Package Update ÿ The following PSPs are currently in development: ARM1020, ARM1026, and ARM1136 MIPS M4K Motorola MPC8540 PMC-Sierra RM7965 ARCtangent - A6 ÿA ÿA ÿA Technical Events >ÿÿ Effective Verification of PQIII based Applications: How to Leverage Co-Verification Mentor Graphics and Motorola Webinar Live webcast: May 21,2003 11am (PST) Bringing up a communications processor as complex, feature-rich and highly integrated as the PowerQUICC III device can be a formidable technical challenge. Fortunately, SeamlessR hardware/software co-verification is already available to help you speed your PowerQUICC III processor-based systems to market. Details and registration: http://www.mentor.com/seamless/seminars/PowerQUICCIII/ ÿ >ÿÿ Design Automation Conference June 2 - 6, 2003 Anaheim, California ÿ DAC 2003 Seamless Hardware/Software Co-Verification for Xilinx Virtex-II Pro Seamless Co-Verification with C-Bridge Platform Express, platform-based design Create, Verify, Analyze, Optimize: The Road to SoC Success System-level Verification - Verifying both the HW and SW in your system - Verisity Register for Technical Presentations at: http://www.mentor.com/dac/sessions.cfm >ÿÿ "Scalable Verification" Luncheon Walden Rhines, Mentor Graphics and Hooman Moshar, Broadcom Tuesday, June 3rd - Noon to 2pm ÿ DAC 2003 Hooman Moshar of Broadcom will present the customer's viewpoint of the design and verification challenges and how they approach solving complex verification problems. Broadcom is a leading provider of highly integrated silicon solutions that enable broadband communications and networking of voice, video and data services. Wally Rhines, Mentor Graphics CEO, will present the functional verification solutions from Mentor Graphics and how they address these key challenges of system verification. ÿ Reservations required. Register at http://www.mentor.com/go/dacevent ÿ >ÿÿ Designers Forum for SoC and IC Engineers Benelux, Eindhoven - June 17, 2003 South of England (near Camberley) - June 25, 2003 A designers forum for engineers involved in digital and analog SoC and IC designs to network providing a rare chance for engineers to exchange ideas, discuss problems and explore solutions. At the event Mentor Graphics and their partners Magma and Verisity will educate and update engineers on the latest advances in EDA design tool technology for verification and layout. For more information and registration: http://www.mentor.com/uk/designersforum ÿ >ÿÿ Mentor Solutions for Designing & Verifying your Xilinx Virtex-II Pro FPGA Mentor Graphics and Xilinx Seminar June 26, 2003: Longmont, CO For more information and registration: http://www.mentor.com/fv/events/seminars/virtexII/ ÿA ÿA ÿA HW/SW Co-Verification Technical Workshops ÿ Seamless Technical Workshop ÿ Scheduled Events: Portland, OR - June 17, 2003 Paris, France - June 18, 2003 Ottawa, Canada - July 8, 2003 El Segundo, CA - July 22, 2003 Irvine, CA - July 24, 2003 Seating is Limited, register at: http://www.mentor.com/seamless/workshops/description.html ÿA ÿA ÿA Press Coverage ÿ Faraday Selects Seamless Co-Verification Faraday Technology Corporation selected the Seamless co-verification environment for the DSP and microcontroller cores in its intellectual properties (IP) library. Learn more - http://www.mentor.com/press_releases/apr03 ÿ Seamless Version 5 Have you heard about Seamless Version 5? The Seamless co-verification environment now includes design performance analysis features such as code profiling as well as bus load, arbitration delay, and memory transaction display windows. Designers can optimize their systems by tuning designs to meet performance metrics and verifying hardware and software interfaces in a single environment. The Seamless product is being used successfully for 32-bit and 64-bit embedded applications in the communications, digital imaging, aerospace, and mass storage market sectors. Learn more - http://www.mentor.com/press_releases/apr03/ Press coverage includes: Performance analysis spots system bottlenecks, Richard Goering - EETimes Up-Front Planning Gets New Attention in EDA, Ed Sperling - Electronic News Mentor sharpens profiles in design, Richard Ball - Electronics Weekly For these articles and more, please visit http://www.mentor.com/seamless/articles/index.html _____ Best Regards, Mentor Graphics Corporation System-Level Verification Division _____ If you do not wish to receive future Seamless News updates, click here (or reply to this email message with "Remove dolinsky@gsu.by" in the subject) Copyrightc 2002 Mentor Graphics Corporation. Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. C-Bridge and Platform Express are trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.