Seamless Hello Michael As you requested, following is your System-Level Verification News Update featuring SeamlessR Co-Verification and Platform ExpressTM, platform-based design. _____ IN THIS DECEMBER ISSUE: New CPU Partnership - ARC International New Technical Paper Product Update - Seamless FPSoC for Xilinx Virtex- II Pro on Linux Technical Events - Co-Verification for Configurable SoC Platforms HW/SW Co-Verification Technical Workshops Press Coverage Other ASIC and SoC Solutions _____ New CPU Partnership - ARC International ÿ Mentor Graphics and ARC have joined forces to provide co-verification model support for the ARCtangent-A4 user-customizable RISC/DSP core. Press Release: http://www.mentor.com/press_releases/dec02/1037907055379.html Partner Datasheet: http://www.mentor.com/seamless/datasheets/index.html Technical Webcast: http://www.mentor.com/seamless/seminars/arct/ New Technical Paper ÿ Creating a Console Within Seamless How can you get printf() to work within Seamless? What are some methods and their merits? How can XRAY be used to implement printf() in the most efficient method possible? This technical paper answers these questions, and provides code examples that you can use in you embedded project. To access this paper and others: http://www.mentor.com/soc/tpapers.cfm Product Update ÿ Seamless FPSoC for Xilinx Virtex-II Pro The Seamless FPSoC for Xilinx Virtex-II Pro is now available on Linux as well as Solaris. Seamless FPSoC for Xilinx Virtex-II Pro combines a special version of the Seamless kernel with a PSP for the PowerPC 405 core that's available on Virtex-II Pro. The bundle is available for $24,000 (US) for a one-year term. Existing Seamless customers may alternatively buy the Xilinx Virtex-II Pro PPC 405 PSP as an option to Seamless. For further information, visit http://www.mentor.com/seamless/fpga or contact your local Mentor account manager. Technical Events ÿ FREE technical presentation - Co-Verification for Configurable SoC Platforms Web Seminar ÿ Improve product quality by fine-tuning the hardware/software interface before tape-out Develop an ASIC with a configurable processor Boost system performance using the ARCtangentTM and SeamlessR Archive available today! http://www.mentor.com/seamless/seminars/arct/ HW/SW Co-Verification Technical Workshops ÿ Seamless Technical Workshop ÿ Scheduled Events: San Diego, CA - January 30, 2003 Cambridge, UK - February 4, 2003 Newbury, UK - February 6, 2003 San Jose, CA - February 18, 2003 Schaumburg, IL - February 19, 2003 Register at: http://www.mentor.com/seamless/workshops/description.html Register for the UK events at: http://www.mentor.com/uk/cuttingedge/prototyping Press Coverage ÿ Support for ARCtangent designs - Seamless from Mentor Graphics offers co-verification model support for ARCtangent user-customizable RISC/DSP designs, December 2002. http://www.mentor.com/press_releases/dec02/1037907055379.html Other ASIC and SoC Solutions ÿ Design-For-Test Solutions - Online Seminar Free Web Seminar ÿÿ Full Flow DFT for ASIC and SoC Designs January 9, 2003 Live Webcast: 10:00 AM (PST) SoC designs require many test methods for the various blocks with these ICs. This seminar demonstrates various test techniques required to test SoCs and how they can be integrated together during DFT insertion and pattern generation. Don't miss this free online seminar! Register now at: http://www.mentor.com/dft/online_reg.cfm _____ Best Regards, Mentor Graphics Corporation System-Level Verification Division _____ If you do not wish to receive future Seamless News updates, click here (or reply to this email message with "Remove dolinsky@gsu.by" in the subject) Copyrightc 2002 Mentor Graphics Corporation. Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. C-Bridge and Platform Express are trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.