Seamless Hello Michael As you requested, following is your System-Level Verification News Update featuring SeamlessR Co-Verification and Platform ExpressTM, platform-based design. _____ IN THIS OCTOBER ISSUE: Product Announcement - Seamless FPSoC for Xilinx Virtex-II Pro Free Online Technical Presentations & Demos Silicon Valley Tech Forum Programmable Logic Users Group - Florida Free hands-on workshops Press Coverage _____ Product Announcement - Seamless FPSoC for Xilinx Virtex-II Pro ˙ Mentor Graphics is pleased to announce Seamless hardware/software co-verification support for the Xilinx Virtex-II Pro family of platform FPGAs embedding the PowerPC 405 processor core. Working in collaboration with Xilinx, we have developed a Seamless solution tailored to the requirements of designers utilizing this solution from Xilinx. Available on November 1st, the Seamless FPSoC for Xilinx Virtex-II Pro package consists of: cycle accurate Seamless Processor Support Package for the PPC405 core and surrounding interface logic; Seamless ready models of the Virtex-II Pro on-chip memories (BRAM); Seamless ready versions of Xilinx reference designs. The initial release will support Verilog simulators, including ModelSim and NC-Verilog, and runs under the Solaris operating system. Support for VHDL, and operation under RedHat Linux will be available shortly. To obtain the datasheet, visit: http://www.mentor.com/seamless/datasheets/seamlessxilinx/Seamless_Xilinx.pdf Free Online Technical Presentations & Demos ˙ >˙˙ Online Presentation and Demo ˙ FREE Web Seminar ˙˙ "SeamlessR Hardware/Software Co-Verification for XilinxR Virtex-II ProTM Platform FPGA" 23 October 2002 Live webcasts: 7:00am and 10:00am (PST) This web seminar will explore: Key features of the Virtex-II Pro Platform FPGA Design tools and flows for Virtex-II Pro Why is co-verification needed in the development of systems using Platform FPGAs? Seamless and its application to the Xilinx Virtex-II Design Flow Details on the Seamless solution configured for use with Virtex-II Pro Registration: http://www.mentor.com/seamless/seminars/xilinx/ ˙ >˙˙ Online Seminar ˙ FREE Web Seminar ˙˙ "Time-to-insight: Early verification of ARMR PrimeXsysTM Platform hardware and firmware" Available Today!!! During this technical session, you will learn how to: Co-verify your embedded PrimeXsys hardware and software prior to tape-out Accelerate verification of PrimeXsys based designs using both RTL and abstract C modeling Registration: http://www.mentor.com/seamless/seminars/primexsys Silicon Valley EDA Tech Forum ˙ Silicon Valley Tech Forum ˙˙ MISSED DAC? Don't miss the Silicon Valley EDA Tech Forum 29 October 2002 - Wyndham Hotel, San Jose California Featuring industry leaders: Gartner Dataquest: Economic Outlook Chartered Semiconductor: Foundry and Design Tool Synchronization Mentor Graphics: Seamless and Platform Express will deliver technical sessions and demos Partner Exhibits: Come visit Denali and Veristy and demo their products supporting Seamless Co-Verification! Register Now: http://www.mentor.com/events/svtf Programmable Logic Users Group ˙ 29 October 2002 Holiday Inn - Clearwater, Florida Technical Sessions and Demos: 8am-5pm Come visit Mentor Graphics at the first Programmable Users Group (PL-UG) Fest sponsored by PL-UG and the Florida West Coast IEEE Computer Society Chapter. Attend a full day of technical presentations for designers and users of FPGA, CPLD, and other programmable devices. We will be presenting on Seamless for Field Programmable System-on-Chip. For more information and registration: http://www.mentor.com/fpga/pl-ug.html Seamless Technical Workshops ˙ Register today for a FREE hands-on workshop to test drive Seamless! FREE Seamless Technical Workshop ˙˙ Meudon-la-ForĒt, France - 5 November 2002 Phoenix, AZ - 5 November 2002 Longmont, CO - 5 November 2002 San Jose, CA - 12 November 2002 Ottawa, Canada - 26 November 2002 Registration: http://www.mentor.com/seamless/workshops/description.html Press Coverage ˙ Re-useable hardware/software co-verification of IP blocks, Electronic Engineering Design by Alistair Bruce, John Goodenough, ARM http://electronicengineering.com/story/OEG20020911S0008 Mixing Abstractions to Speed Design and Verification of Embedded Systems, John Blyler's Software Solutions eletter by Eric Johnson, Mentor Graphics Find this article and others at http://www.mentor.com/seamless/articles/index.html _____ Best Regards, Mentor Graphics Corporation System-Level Verification Division _____ If you do not wish to receive future Seamless News updates, click here (or reply to this email message with "Remove dolinsky@gsu.by" in the subject) Copyrightc 2002 Mentor Graphics Corporation. Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. C-Bridge and Platform Express are trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.