Welcome to IEEE TCCA Email-Monthly, June 2005. 1. IISWC-2005: IEEE International Symposium on Workload Characterization *October 6-8, 2005, Austin, Texas *Abstract submissions: June 20, 2005 *Submitted by: Suleyman Sair *Call for Papers: http://www.iiswc.org/iiswc2005/ 2. HPCA-12 12th Int'l Symposium on High-Performance Computer Architecture *February 11-15, 2006, Austin, Texas, *SUBMISSION DEADLINE: July 11, 2005 *Submitted by: Ki Hwan Yum *Call for Papers: http://www.hpcaconf.org/hpca12 3. ASPLOS XII: 12th International Conference on Architectural Support for Programming Languages and Operating Systems *October 21st - 25th, 2006, San Jose, CA *SUBMISSION DEADLINE: March 8, 2006 *Submitted by: Li-Shiuan Peh *Call for Papers: http://www.princeton.edu/~asplos06 4. HiPEAC 2005: Int'l Conference on High Performance Embedded Architectures & Compilers *Barcelona, Spain, 17-18 November 2005 *SUBMISSION DEADLINE EXTENDED TO JUNE 17, 2005 *Submitted by: Sally McKee *Call for Papers: http://www.hipeac.net/hipeac2005 5. SNAPI'05: Int'l Workshop on Storage Network Architecture and Parallel I/Os *Saint Louis, Missouri, September 18, 2005 *SUBMISSION DEADLINE: July 10, 2005 *Call for Papers: http://rcf.unl.edu/~abacus/SNAPI_05/ ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ 2005 IEEE International Symposium on Workload Characterization IISWC-2005 October 6-8, 2005 Austin, Texas Call for Papers Important Dates Abstract submissions: June 20, 2005 Final Paper submission: June 27, 2005 Acceptance Notified: August 26, 2005 Final Manuscript Submission: September 7, 2005 Topics of Interest Papers are solicited in all areas related to characterization of workloads (system and/or application behavior) in a variety of environments. Topics of interest include (but not limited to): * Workload characterization or related studies focusing on the following types of applications: o E-commerce, Web server, Database o Embedded, Mobile, Multimedia o Life Sciences, Drug Discovery o Java, Object-oriented o Learning and Discovery, Graphics o Multiprocessor o Scientific and technical o Security, Biometrics o Operating system intensive o Multi-threaded * Effects of architectural features on workload behavior * Machine independent characterization of workloads * Memory and I/O access patterns * Power and reliability issues related to workload * Benchmark creation and validation * Representative trace generation * Profiling, trace collection and validation issues * Workload synthesis * Abstract modeling of program behavior * Emerging and Future workloads For further information, please contact the Program or General Chair: General Chair Lizy John, The University of Texas at Austin Program Chair David Kaeli, Northeastern University kaeli@ece.neu.edu ------------------------------------------------------------------------- HPCA-12 Call for Papers 12th International Symposium on High-Performance Computer Architecture Austin, Texas, February 11-15, 2006 http://www.hpcaconf.org/hpca12 The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: * Processor architectures * Cache and memory systems * Parallel computer architectures * Impact of technology on architecture * Power-efficient architectures and techniques * High-availability architectures * High-performance I/O systems * Embedded and reconfigurable architectures * Interconnect and network interface architectures * Network processor architectures * Innovative hardware/software trade-offs * Impact of compilers on architecture * Performance evaluation of real machines Authors should submit an abstract before Monday, July 11, 2005, 9pm PST. They should submit the full version of the paper before Monday, July 18, 2005, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in http://www.hpcaconf.org/hpca12 Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations. Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution. New-idea papers are encouraged. Submission issues should be directed to the program chair at das@cse.psu.edu. Workshop and tutorial submissions should be directed to the workshop and tutorial chair. Important dates * Abstract submission deadline : July 11, 2005, 9pm PST (firm deadline) * Paper submission deadline: July 18, 2005, 9pm PST (firm deadline) * Workshop and tutorial proposals due: August 12, 2005 * Author notification: October 7, 2005 Sponsored by the IEEE Computer Society TC on Computer Architecture General Co-Chairs: Yale Patt, UT Austin Craig Chase, UT Austin Program Chair: Chita R. Das, Penn State Program Committee: Laxmi Bhuyan, UC Riverside Ricardo Bianchini, Rutgers Univ. David Brooks, Harvard Doug Burger, UT Austin Derek Chiou, UT Austin Frederic T. Chong, UC Davis Dan Connors, Colorado Tom Conte, NCSU Srini Devadas, MIT Jose Duato, Univ. Politecnica Valencia Michel Dubois, USC Rajiv Gupta, Arizona James C. Hoe, CMU Ravi Iyer, Intel Mahmut Kandemir, Penn State Eun Jung Kim, Texas A&M Mikko Lipasti, Univ. of Wisconsin Kai Li, Princeton Scott Mahlke, Michigan Randy Moulic, IBM T.J. Watson Trevor Mudge, Michigan Ashwini Nanda, IBM T.J. Watson Vijaykrishnan Narayanan, Penn State Mark Oskin, Washington Dhabaleswar K. (DK) Panda, OSU Sanjay Patel, UIUC Li-Shiuan Peh, Princeton Milos Prvulovic, GATECH Michael Shebanow, NVIDIA Anand Sivasubramaniam, Penn State Per Stenstrom, Chalmers University of Technology Josep Torrellas, UIUC Dean M. Tullsen, UCSD Mateo Valero, Univ. Politecnica Catalunya Pen-Chung Yew, Minnesota Qing Yang, Rhode Island Raj Yavatkar, Intel Mazin Yousif, Intel Yuanyuan Zhou, UIUC Industry Liaison Chair: Mazin Yousif, Intel Local Arrangements Chair: Derek Chiou, UT Austin Workshop and Tutorial Chair: Yan Solihin Publicity and Publications Chair: Ki Hwan Yum, UT San Antonio Finance and Registration Chair: Craig Chase, UT Austin Web Chair: Vijaykrishnan Narayanan, Penn State Steering Committee: Dharma Agrawal, Univ. of Cincinnati Laxmi Bhuyan, Univ. of California, Riverside Jean-Luc Gaudiot, Univ. of California, Irvine Yale Patt, UT Austin Josep Torrellas, UIUC Justin Rattner, Intel ------------------------------------------------------------------------- C A L L F O R P A P E R S ASPLOS XII (12th International Conference on Architectural Support for Programming Languages and Operating Systems), San Jose, CA October 21st - 25th, 2006 http://www.princeton.edu/~asplos06 Sponsors: SIGARCH, SIGPLAN, SIGOPS, Intel Corporation, Microsoft Corporation ASPLOS is a multi-disciplinary conference that seeks cross-cutting research in the areas of hardware, architecture, compilers, operating systems, networking, and applications. It has captured some of the major computer systems innovations of the past two decades (e.g., RISC and VLIW processors, small and large-scale multiprocessors, clusters and networks-of-workstations, optimizing compilers, RAID, and network-storage system designs). Today, multi-disciplinary research is becoming even more important, as boundaries between hardware/software and local/network computing blur and as the form and capabilities of computing devices becomes ever more varied. Like its predecessors, the ASPLOS 2006 conference will focus on ground-breaking research, particularly efforts focusing on the interplay of hardware and software systems. The program committee welcomes research papers on a wide range of non-traditional topics that emphasize the multi-disciplinary aspects of their work. Full papers are solicited on, but not limited to, these topics: - Interaction of operating systems, compilers, programming languages, and architectures - Hardware/software issues for new platforms, from sensor networks to wireless PDAs to wall-sized displays - Hardware/software issues focusing on Internet services - Hardware/software platforms for delivering graphics and multimedia - Embedding computation and storage (e.g., caches) within networks - Case studies of hardware/software design in novel experimental systems - Studies of Internet applications and services with implications for systems design - Security and availability issues for current/future computer systems - Evaluations of experimental systems for performance, power, availability. - Effect of technology and application drivers on architectures, operating systems, or compilers The program committee and designated reviewers will read all submissions using a double-blind system, evaluating them based on scientific merit, innovation, relevance, and presentation. ``New-idea'' papers are encouraged; they will be considered with particular regard for the difficulties of performing thorough evaluations in less-established areas. The committee will also give special consideration to controversial papers that stimulate interesting debate during the committee meeting. Accepted papers will be published in a conference proceedings that will be distributed at the conference and published as an issue of the ACM SIGARCH, SIGOPS and SIGPLAN newsletters. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work. ***Important Dates and Deadlines*** Full Papers Due: March 8, 2006 Author Notification: June 1, 2006 Final Papers Due: July 31, 2006 General Co-Chairs: John Shen, Intel Corp. Kunle Olukotun, Stanford Program Chair: Margaret Martonosi, Princeton Univ. Steering Committee: Norm Jouppi, HP Labs James Larus, Microsoft Corp. Keith Marzullo, UC San Diego Kathryn S. McKinley, U. Texas Shubu Mukherjee, Intel Corp. Larry Peterson, Princeton University Workshops and Tutorials: Ras Bodik, UC Berkeley Wild and Crazy Ideas Session: Mark Oskin, Univ. of Washington Publications: Chen Ding, University of Rochester Publicity: Li-Shiuan Peh, Princeton University Finance Chair: Scott McFarling, Intel Corp. Registration: Lance Hammond, Stanford Local Arrangements: Quinn Jacobson, Intel Corp. Conference Coordinator: Trisha Zamora, Intel Corp. ------------------------------------------------------------------------- **** SUBMISSION DEADLINE EXTENDED TO JUNE 17 **** HiPEAC 2005 2005 International Conference on High Performance Embedded Architectures & Compilers Barcelona, Spain, 17-18 November 2005 The embedded market evolves rapidly, expanding the capabilities of each new device, and making the previous ones obsolete as technology advances. In order to achieve the high performance required by new embedded applications, these embedded processors are increasingly high-performance processors, with an increasing overlap between general-purpose and embedded processors. However, performance does not simply increase with technology advances, it is essential to find a way to translate technology into performance, and such is the role of the computer architect and compiler builder. The HiPEAC conference provides a high-quality forum for computer architects and compiler builders working in the field of high performance computer architecture and compilation for embedded systems, but is also open to general-purpose research which is becoming increasingly relevant to the embedded domain. The conference aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. Topics of interest include, but are not limited to: - Processor architectures - Memory system, code size/memory footprint optimizations - Power, performance and implementation efficient designs - Network processors - Security processors - Application specific processors and accelerators - Reconfigurable architectures - Simulation and methodology - Compiler techniques - Feedback-directed optimization - Program characterization and analysis techniques - Dynamic compilation, adaptive execution, and continuous profiling/optimization - Back-end code generation - Binary translation/optimization Conference Web Site: http://www.hipeac.net/hipeac2005 HiPEAC 2005 is collocated right after MICRO-38, The 38th Annual IEEE/ACM International Symposium on Microarchitecture, Barcelona, Spain, November 12-16, 2005 http://www.microarch.org/micro38 ***PAPER SUBMISSION DEADLINE: June 17, 2005 **** Submission details and all information concerning the symposium can be found at the conference web site. Acceptance/rejection will be emailed by August 5, 2005. The final manuscript will be due September 10, 2005. General Co-Chairs Tom Conte, NC State University, USA Nacho Navarro, UPC, Spain Program Committee Co-Chairs Mateo Valero, UPC, Spain Wen-mei W. Hwu, UIUC, USA Program Committee David August, Princeton University, USA David Bernstein, IBM Haifa Research Lab, Israel Mike O'Boyle, University of Edinburgh, UK Brad Calder, University of California, USA Jesus Corbal, Intel Labs Barcelona, Spain Alex Dean, NC State University, USA Koen De Bosschere, Ghent University, Belgium Jose Duato, UPV, Spain Marc Duranton, Philips, France Kristian Flautner, ARM Ltd., Cambridge, UK Jose Fortes, University of Florida, USA Roberto Giorgi, Universita di Siena, Italy Rajiv Gupta, University of Arizona, USA Kazuki Joe, Nara Women's University, Japan Manolis Katevenis, ICS, FORTH, Greece Stefanos Kaxiras, University of Patras, Greece Victor Malyshkin, Russian Academy of Sciences, Russia William Mangione-Smith, UCLA, USA Avi Mendelson, Intel, Israel Enric Morancho, UPC, Spain Jaime Moreno, IBM TJ Watson Research, USA Andreas Moshovos, University of Toronto, Canada Trevor Mudge, The University of Michigan, USA Alex Nicolau, University of California, USA Yale Patt, The University of Texas at Austin, USA Antonio Prete, University of Pisa, Italy Alex Ramirez, UPC, Spain Jim Smith, University of Wisconsin, USA Per Strenstrom, Chalmers University, Sweden Olivier Temam, INRIA Futurs, France Theo Ungerer, University of Augsburg, Germany Stamatis Vassiliadis, T.U. Delft, The Netherlands Jingling Xue, University of New South Wales, Australia Publicity Chair Sally A. McKee, Cornell University, USA Publication Chair Theo Ungerer, University of Augsburg, Germany Local Arrangements Co-Chairs Eduard Ayguade, UPC, Spain Josep Llosa, UPC, Spain Registration/Finance Chair Pilar Armas, UPC, Spain Web Chair Michiel Ronsse, Ghent University, Belgium Steering Committee Anant Agarwal, MIT, USA Koen De Bosschere, Ghent University, Belgium Mike O'Boyle, University of Edinburgh, UK Brad Calder, University of California, USA Rajiv Gupta, University of Arizona, USA Wen-mei W. Hwu, UIUC, USA Josep Llosa, UPC, Spain Margaret Martonosi, Princeton University, USA Per Stenstrom, Chalmers University, Sweden Olivier Temam, INRIA Futurs, France _______________________________________________ ------------------------------------------------------------------------- International Workshop on Storage Network Architecture and Parallel I/Os To be held with the 14th International Conference on Parallel Architectures and Compilation Techniques, Saint Louis, Missouri Data are the "life-blood" of computing and the main asset of any organization. T herefore, disk I/O and data storage on which data reside are becoming "first cla ss citizens" in today's information world. This workshop intends to bring togeth er researchers and practitioners from academia and industry to discuss cutting e dge research on parallel and distributed data storage technologies. By discussin g ongoing research, the workshop will expose participants to the most recent dev elopments in storage network architectures and parallel I/O. Topics of interest include but are not limited to: 1. Storage Manageability, Reliability, Availability, and Security 2. Storage Performance and Scalability 3. File systems, Object-based storage, block-level storage 4. NAS and SAN architectures 5. Storage networking: e.g. Fibre Channel, InfiniBand, IP Storage, iSCSI 6. Parallel I/O architectures 7. Caching and consistency 8. Evaluation of storage architectures 9. Storage management software Organizer: Qing (Ken) Yang Dept. of ECE University of Rhode Island Kingston, RI 02881 Email: qyang@ele.uri.edu Tel: 401-874-5880 Fax: 401-782-6422 Co-Organizer Hong Jiang Dept. of CSE University of Nebraska - Lincoln Lincoln, NE 68588-0115 USA Phone: 402-472-6747 Fax: 402-472-7767 E-mail: jiang@cse.unl.edu ------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe