ïÔ: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
ïÔÐÒÁ×ÌÅÎÏ: 16 ÎÏÑÂÒÑ 2004 Ç. 13:13
ëÏÍÕ: Michael Dolinsky
ôÅÍÁ: D&R SoC News Alert - November 16, 2004
DR SoC News Alert
Design And ReuseDesign And ReuseDesign And Reuse
EETimes Network
November 16, 2004    


Michael,

Welcome to issue of November 16, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.


SPONSORED BY: TRUE CIRCUITS, INC.

True Circuits, Inc. offers a family of award-winning clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC and FPGA designers.
These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
Call (650) 691-2500 or visit http://www.truecircuits.com/dr9.

IEEE 802.16d OFDM-256 baseband PHY (Optimized for SOC & FPGA) from SiWorks
MPEG-2 Main Profile @ Main level video encoder/decoder for Texas Instruments DSP from Ateme
SD/SDIO/MMC Host Controller from ASICS World Services
FIR core generator optimized for use with Actel's flash- and antifuse-based families of FPGAs from Actel
MIMO Bluetooth 2 × 2 MIMO FSK Coder / Decoder Module from Comsis
GSM-AMR Audio Encoder/Decoder Software IPs from Hantro
CPRM Crypter from Arasan Chip Systems
Wanted IPs :
  • reference price for following IPs: 1)Scaler 2)De-interlace 3)Video quality enhancement
  • 3D Graphics Accelerator
  • 2D Graphics Accelerator
  • CABAC encoder for H264 in FPGA
  • 802.16 (WiMAX) Matlab/C testbench
  • Power Islands: The Evolving Topology of SoC Power Management
    How platform-based design cuts digital still camera design time and costs
    A practical view of ESL design
    No size fits all for signal processing on FPGA (RF Engines)
    Relational physical design: no absolutes (ReShape)
    Why full-chip formal verification is possible
    IP/SOC PRODUCTS
    CEVA Shatters Performance Record for Licensable DSP Core With CEVA-X
    Altera and PLDApplications Announce First FPGA PCI Express Solution to Pass All PCI-SIG Compliance and Interoperability Tests
    Actel Expands IP Offering with New High-Performance DDR Memory Controller Core
    austriamicrosystems launches field-programmable OTP memory solution
    Hardware-independent Bluetooth software offers low-cost platform for next-generation portable devices
    STRUCTURED ASIC
    Denali Software Announces Membership in LSI Logic RapidChip Partner Program
    Thirteen Third-Party IP, Design Services and EDA Tool Suppliers Announce Support of LSI Logic's Rapidchip
    GDA Technologies announced that is has joined the LSI Logic RapidChip Partner Program
    DEALS
    Spreadtrum Launches World's First Chinese 3G Chipset Powered By CEVA-Teak DSP Core
    CEVA Licenses Xpert-Teak DSP Platform To Sharp For Portable Multimedia Devices
    Epson Selects Tensilica's Xtensa Processor
    MIPS Technologies Licenses Highest-Performance 32-Bit Core to TZero
    Aarohi Delivers ARC-Based FabricStream Intelligent Storage Processor to Customers
    BUSINESS
    IPCore Adds TriCN to IP Provider List
    AMI Semiconductor Completes Acquisition of Dspfactory Ltd.
    ARM to establish design center in India
    SMSC and TransDimension Team to Achieve First USB-IF Certification of ULPI Controller and Transceiver
    LEGAL
    Patriot Scientific Corporation (PTSC) clarifies rejection announcement of offer for microprocessor patent portfolio
    VIA to license 3Com patents
    Patriot Scientific Rejects Offer for Microprocessor Patent Portfolio
    Infineon and ProMOS reach agreement regarding licenses to ProMOS - Infineon to receive licence fees of US-Dollar 156 million
    PEOPLE
    Denali's Sanjay Srivastava Named to EDA Consortium Board of Directors
    Altera Consolidates Marketing Departments
    Steven Laub Appointed As President & CEO of Silicon Image
    EMBEDDED SYSTEMS
    NEC Engineering Launches ZigBee™-Ready Wireless Network Module with NEC Electronics 78K0 Microcontroller and Chipcon CC2420 RF Transceiver Chip
    LSI Logic Launches Most Comprehensive Offering Of Voice-Over-Ip Solutions
    Video Infrastructure Development Eased with ATEME's NVDK
    Sharp Microelectronics ARM9 32-bit SoCs Now Available with OSE 5.0 Operating System
    FOUNDRIES
    Tower Semiconductor Announces Cost Reduction Plan
    AMD and Chartered sign sourcing and manufacturing technology agreements
    TSMC October Sales Report
    FPGA/CPLD
    Lattice Introduces New Evaluation Platforms for LatticeEC FPGAs
    Xilinx Solves Memory Interface Design Challenges With Virtex-4 Memory Development System
    FABLESS
    Zoran Corporation Announces New Multimedia Solutions For Mobile Phones
    Nordic Semiconductor Launches the nRF2401A, Upgrading the Industry Leading nRF2401 2.4GHz Transceiver with even Lower Cost and Improved Performance
    EDA
    CoWare and Forte Deliver First Integrated SystemC-based Solution For Electronic System Level (ESL) Design to Implementation
    Applied Micro Circuits Corporation (AMCC) Standardizes on Verisity's VPA Platform
    Altium takes "Low-RISC" approach to 32-bit system development on FPGAs
    OTHER
    Ateme participates in MPEGIF's H.264 interoperability tests
    Multiband OFDM Alliance releases UWB PHY specs
    Microprocessor consortium to add energy spec

    SPONSORED BY: TEMENTO SYSTEMS

    Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

    Click here to know more about Temento


    IP/SOC 2004
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    December 8-9, 2004


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