От: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
Отправлено: 9 ноября 2004 г. 15:31
Кому: Michael Dolinsky
Тема: D&R SoC News Alert - November 9, 2004
DR SoC News Alert
Design And ReuseDesign And ReuseDesign And Reuse
EETimes Network
November 9, 2004    


Welcome to issue of November 9, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: TRUE CIRCUITS, INC.

True Circuits, Inc. offers a family of award-winning clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC and FPGA designers.
These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
Call (650) 691-2500 or visit http://www.truecircuits.com/dr9.

NAND Flash Controller from Eureka Technology
Complete 802.11a/g OFDM Baseband Modem from Wavebreaker AB
WLAN baseband AFE (802.11abg), 10-bit/80MHz (DAC @40MHz), with PLL and voltage regulator from ChipIdea Microelectronics
Standard Cells TSMC 130nm (CL013G) - Mobilize Power Management IP from Virtual Silicon
Windows Media 9 audio/video encoder/decoder for C64x, DM642 from Ateme
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro from Soft Mixed Signal
ZenTime, a Design Optimization Tool for standard cell-based designs from Zenasis Technologies
Wanted IPs :
  • 10/100 Ethernet DSP PHY
  • SONET OC-12 & OC-3 Serializer/Deserializer IP
  • Modeling Total Cost of Ownership for Semiconductor IP (Synopsys)
    Navigating the Reef: Supplying IP That Works For You and Your Customer (Zarlink Semiconductor)
    Getting an algorithm ready for reuse (eInfochips)
    Reality check for configurable IP blocks (IPextreme)
    Verification issues for reconfigurable IP (Actel)
    True reuse moves well beyond recycling (VSIA)
    Reuse of Analog Mixed Signal IP for SoC Design: Progress Report (Cadence Design Systems)
    Achieving Reuse with both Modifiable IP and Configurable IP (LSI Logic)
    Like it or not, IP's here to stay
    IP/SOC PRODUCTS
    PLD Applications' PCI-SIG-tested x1, x4, x8 PCI Express IP Core validated for FPGA and ASIC integration
    Ignios, a recent entrant in the embedded multicore System-on-Chip (SoC) market, announces first product availability
    CPU Tech announces World's first configurable family of true 64-bit processor cores for Deeply Coupled Computing
    ARM, Artisan, National Semiconductor, Synopsys and UMC Collaborate On Comprehensive Low-Power SoC Solution
    Actel Offers High-Performance, Easy-to-Use FPGA-Based DSP Solution
    STRUCTURED ASIC
    eASIC Successfully Qualifies Structured eASIC in 0.13 micron Silicon
    DEALS
    Toshiba Licenses ARM11 Family Processor
    Japan's Dai Nippon Printing Uses ARM Technology To Develop Java Card OS
    Atmel Powers Next-Generation High Performance Storage Applications by Licensing Industry-Leading CEVA-X DSP
    Analog Devices and SiWorks Announce Agreement to Develop a Flexible Modem Solution for 802.16 WiMAX Forum Base Stations
    Thomson and ARM Strengthen Their Integrated Circuit Strategies Through OptimoDE Partnership
    BUSINESS
    True Circuits Selects Amos Technologies to Distribute Its Silicon-Proven Timing Intellectual Property
    CEVA Launches CEVAnet Partner Program To Extend DSP Offerings And Deliver Complete Solutions
    ST preaches new 'Gospl' (Generalized Open Source Programmable Logic) for programmable logic
    SynTest Signs QualCore Logic as Distribution Partner for India
    Integrated Circuit Designs (ICD) completes $2M round of private funding
    Synopsys Acquires Assets of LEDA Design
    FINANCIAL RESULTS
    Faraday Announced Revenue for October; Record Revenue of NT$460Million
    Aware, Inc. Reports 2004 Third Quarter Financial Results
    LEGAL
    Toshiba files memory patent suits against Hynix
    EMBEDDED SYSTEMS
    Agere Systems Unveils Industry's First Single-Chip 48-Port Gigabit Ethernet Switch and Lowest Power Octal PHY
    GDA Technologies announces availability of Dual G4 cPCI Single Board Computer
    Hantro demonstrates H.264/AVC player in 'Off-the-Shelf' Mobile Handset
    TI India working on single-chip solution for mobile phones
    FOUNDRIES
    China to build five 300-mm wafer fabs by 2006
    FPGA/CPLD
    Xilinx Delivers Industry's Lowest Power FPGAs With New Sparan-3L Family
    Xilinx Unveils New CoolRunner-II CPLDs For Price-Sensitive Small Form-Factor Applications
    Cypress Qualifies its PSoC Mixed-Signal Array for Automotive Applications
    EDA
    New Release of CoWare ConvergenSC Speeds Adoption of Electronic System Level (ESL) Design
    CoFluent Design helps designers take the right decisions at the right time; CoFluent Studio enables designers to get accurate models of hardware/software systems in projects' first 20%
    TransEDA Code Coverage Tool Integrated with Verisity's vManager to Boost Verification Productivity for Mixed-Language Designs
    OTHER
    LSI Logic Announces Webcast Of RapidChip Platform ASIC Partner Program Presentations
    MindTree to Exhibit its Bluetooth Solutions for Mobile Telephony at WiCon Americas

    SPONSORED BY: TEMENTO SYSTEMS

    Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

    Click here to know more about Temento


    IP/SOC 2004
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    December 8-9, 2004


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