От: D&R SoC NewsAlert [SoC-NewsAlert@design-reuse.com]
Отправлено: 12 октября 2004 г. 13:00
Кому: Michael Dolinsky
Тема: D&R SoC News Alert - October 12, 2004
DR SoC News Alert
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October 12, 2004    


Welcome to issue of October 12, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: TRUE CIRCUITS, INC.

True Circuits, Inc. offers a family of award-winning clock generator, deskew, low-bandwidth and spread-spectrum PLLs and DDR DLLs that spans nearly all performance points and features typically requested by ASIC and FPGA designers.
These high-quality, low-jitter, silicon-proven hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25um to 90nm.
Call (650) 691-2500 or visit http://www.truecircuits.com/dr9.

SATA Host from Synopsys
A complete 802.11a/b/g direct conversion transceiver from Wavebreaker AB
Ultra-High Throughput GCM-AES Core (40 Gbps) from Elliptic Semiconductor
3.14 Megapixel Camera Interface from sci-worx GmbH
Pipelined FFT cores, sample rates to GS/s, transform lengths to 128M points from RF Engines
High-performance/power-efficient quad-MAC/six-ALU DSP core from LSI Logic Corporation
ARINC 429 Bus Interface from Actel Corp.
PCI Express Switch Port Controller from GDA Technologies
MPLS & VPLS Solutions, OSPF Protocol Stack, Border Gateway Protocol & Ethernet Switch software solution from Wipro Technologies
USB2.0 OTG LS-FS-HS 3.3-1.2-1.0 UTMI+ on TSMC 90nm from ChipIdea Microelectronics
Selecting PLLs for ASIC Applications Requires Tradeoffs
OCP-based Memory Controller IP Offers Optimal Power and Performance Requirements for 3G Applications
RF integration: Changing the face of test
Process Improvements for System on Chip developments
Restoring predictability in SoC integration
Integrating High Speed Serial Transceivers into an FPGA
IP reuse simplifies SoC design, verification
Designing an optimal wireless SoC
IP Cores for FPGAs
Configurable Processors for Video Processing SOCs
Complex chips reignite demand for design services
Design complexity drives need for ESL
ARM's Neon: Too late to the portable party?
FSA panel debates crosstalk doom
IP/SOC PRODUCTS
Industry's Highest-Performance Cores Just Got Faster with Release of Enhanced MIPS32 24K Core Family
ARC Simplifies Processor Configurations
PDF Solutions and Virage Logic Partner to Create Process-Aware Semiconductor IP Libraries
LSI Logic Unveils Highly Efficient Quad-MAC DSP Core Targeting Advanced Mobile Multimedia Applications
Elliptic Semiconductor Launches Ultra Fast Link Security Product for Ethernet and Optical Transmission
Chipidea and Tower achieve certification for USB 2.0 OTG
MOSAID Launches Programmable Memory BIST
LTRIM's LTR1010 Low Dropout Voltage Regulator Lowers Power Consumption, Increases Battery Life of Portable Devices
STRUCTURED ASIC
eASIC Ranked #1 Logic & Programmable Logic - Ultimate Product in a Survey of over 1,300 Engineers
Faraday Unveils Highest Performance NPU with Structured ASIC Programmability for Less Than $50
DEALS
Conexant Licenses ARC Configurable Processor Core
Actel Announces License Agreement with Motorola for DirectCore IP and FPGAs
BUSINESS
Jennic Adopts Fabless Semiconductor Business Model
FINANCIAL RESULTS
Faraday Announces Revenue for September Record Revenue of NT$450Million
DESIGN SERVICES
NetEffect selects GDA Technologies Inc as the Design services partner for next generation Multi Gigabit Ethernet solution
iRoC Technologies Introduces SERPRO Services for Transistor-level Soft Error Rate Analysis and Optimization
EMBEDDED SYSTEMS
MIPS-Based Products at Fall Processor Forum Raise the Bar on Next-Generation Embedded Systems
FOUNDRIES
SMIC confirms 90-nm foundry technology plans
Foundries face inventory correction, then downturn
TSMC September Sales Report
Matsushita, Tower deploying 0.18-micron embedded flash
austriamicrosystems' industry leading CMOS High Voltage process now available for foundry customers
FPGA/CPLD
TANDBERG Television Adopts Altera Stratix II Devices and Nios II Embedded Processors to Deliver DVB-ASI
Intellectual Property Support for New Lattice FPGAs Grows Rapidly
Lattice Semiconductor Announces Production Release of New Low-Cost FPGA Products
EDA
Synopsys says it will shelve Monterey's tools
OTHER
Freescale embraces IMEC multiprocessor approach

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento






IP/SOC 2004
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December 8-9, 2004


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