Hello Michael As you requested, following is your SoC Design and Co-Verification News Update featuring Platform Express™ for platform-based design and Seamless® and Seamless FPGA for hardware/software co-verification. In this issue: Enabling Innovation Seminars Online Seminar eScape to SystemVerilog Seminars Technical Publications Seamless Hands-On Workshop Seamless FPGA Evaluation Software

	Enabling Innovation Seminars
	ARM/LSI Logic/Mentor Graphics seminars Enabling Innovation: SoC Design and Verification Solutions from the Industry Leaders Successful development of System-on-Chips (SoCs) doesn't just happen. There needs to be the right IP, the right methodologies, and trusted partners. If all of these exist, an SoC customer is empowered to develop the innovative solutions that today's markets demand. During this half-day seminar, ARM, LSI Logic, and Mentor Graphics will present how to create the foundations for SoC success. Dates and Locations: May 17 - Irvine, CA May 19 - Santa Clara, CA Visit the Mentor Graphics website for more information and to register for this exciting event.

	Online Seminar
	Your Design: Boot it before you build it During this short presentation, you will learn more about Seamless, the Mentor Graphics hardware/software co-verification solution. We will discuss the goals of co-verification and the best time to conduct it, both for hardware and software. We also look at performance analysis of software, memory, and bus characteristics. Watch the archived seminar today.

	eScape to SystemVerilog Seminars
	Interest in the use of SystemVerilog for verification is strong. Not surprisingly, many organizations that have led the evolution in verification by using the proprietary HVL e, are exploring a move to standards and SystemVerilog. This seminar provides guidance on transitioning to SystemVerilog for verification by showing and contrasting language capabilities and how common verification structures and techniques are implemented in both languages. This seminar will be particularly valuable to those using Verisity®'s e language. Learn practical and up-to-date guidance on transitioning to a standards-based verification methodology built on SystemVerilog. Visit our website for more details.

	Technical Publications
	Migrating Software to Hardware on FPGAs Seamless FPGA Speeds Verification for Xilinx Virtex-4 and Virtex-II Pro FPGAs Measuring and Tuning Real-Time Performance of Embedded Systems Functional Verification Technology and Methodology Backgrounder Check out the entire archive of technical papers.

	Seamless Hands-On Workshop
	Hardware/Software Co-Verification workshop Date and Location: May 24 - Austin, TX Find out more and register for this upcoming workshop.

	Seamless FPGA Evaluation Software
	Learn more about Seamless FPGA. Watch an online seminar or a multimedia demo or download the software to evaluate it for 30 days. Online seminar: Verification of your Embedded FPGA Design Multimedia demo Seamless FPGA evaluation

Best Regards, Mentor Graphics Corporation SoC Design and Verification Division http://www.mentor.com/products/fv/hwsw_coverification/index.cfm

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