От: seamless_info@mentorg.com
Отправлено: 2 декабря 2004 г. 21:22
Кому: Michael Dolinsky
Тема: SoC Design and Co-Verification eNews
Seamless


Hello Michael

As you requested, following is your SoC Design and Co-Verification News Update featuring Platform Express™ for platform-based design, Seamless® for hardware/software co-verification, and Seamless ASAP for system optimization.




IN THIS ISSUE:


Live Web Seminar
Full System Verification and Analysis for the StarCore SC1000 and Family of Processors
December 9, 2004: 10am US Pacific / 1pm US Eastern / 6pm UK
 
Technical Publications Available
  • New  Measuring and Tuning Real-Time Performance of Embedded Systems
  • Seamless FPGA Speeds Verification for Xilinx Virtex-4 and Virtex-II Pro FPGAs with Embedded IBM PowerPC Processors (written by Xilinx)
Check out the entire archive of technical papers available.
 
Archived Web Seminars
View all archived online seminars
 
Articles and Press
»   Articles
  • A Practical View of ESL
  • IP Reuse Simplifies SoC Design, Verification
  •  
    »   Press
  • November 9 - Atmel Corporation and Mentor Graphics Extend and Expand Partnership
  • November 8 - CEVA Launches CEVAnet Partner Program To Extend DSP Offerings And Deliver Complete Solutions
  •  
      Feedback
    We would appreciate any feedback you have regarding this newsletter's content.
     
    Return to Top
     



    Best Regards,

    Mentor Graphics Corporation
    SoC Design and Verification Division
    http://www.mentor.com/products/fv/hwsw_coverification/index.cfm



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