Hello Michael As you requested, following is your SoC Design and Co-Verification News Update featuring Platform Express™ for platform-based design, Seamless® for hardware/software co-verification, and Seamless ASAP for system optimization. IN THIS ISSUE: New: Seamless FPGA Events Lunch and Learn Seminars Online Seminars EDA Tech Forums ARM Developer's Conference PSP Update Call for Papers Partner Update Co-Verification CD Technical Publications Seamless FPGA Seamless FPGA is a new co-verification product for Xilinx FPGAs with PowerPC processors. Seamless FPGA combines debug capabilities, simulation performance, and faster iteration cycles to speed design completion. Download free evaluation software! Find out more. Global Events »   Lunch and Learn Seminars Faster Completion of your Embedded Xilinx Design October 12 - San Jose, CA October 13 - Waltham, MA October 14 - Ottawa, ON Find out more and register today!   »   Live online seminar Eliminate Performance Bottlenecks in Embedded Designs November 2, 2004 at 10am US Pacific / 6pm UK   »   Online seminar archives Verification of your Embedded FPGA Design (presented by Mentor Graphics and Xilinx) Rapid AMBA-Based SoC Design using Platform Express (presented by ARM and Mentor Graphics) View all archived online seminars.   »   EDA Tech Forums The EDA Tech Forum offers attendees the opportunity to learn about the latest technology trends and challenges facing the EDA design community. The Forums include industry expert keynotes, industry panels, hands-on workshops and technical tracks! Each event has specialist sessions for embedded system design and co-verification. October 18 - San Jose, CA November 17 - Dallas, TX Find out more about these events.   »   ARM Developer's Conference Santa Clara, CA Visit the Mentor Graphics booth #214 to see a demo or come see a presentation: Maximize the Throughput of your ARM Design October 19, 2004 - 1:00-1:40 Application Optimization through the Use of ARM Core-Based Co-processors October 20, 2004 - 4:10-5:00 PSP Update Seamless for hardware/software co-verification supports more than 100 Processor Support Packages (PSP). Visit us to find a complete list. New PSPs added include: ARM: ARM968E-S CEVA: Teak - architecture revision 1.7/1.71, RTL version 2.2 LSI Logic: ZSP500 StarCore: SC1200 and SC1400 Call for Papers The 2005 Mentor Graphics International User Conference - User2User - will be a highly interactive, in-depth technical conference for the exchange of immediately useful knowledge between all Mentor Graphics users, and with Mentor Graphics technical leaders and partners. Benefits of presenting include the opportunity to win $1000 for the best paper award, free conference registration, speaker gift and more. All valid abstracts received by October 8, will be eligible for one of three prizes donated by HP - IPOD + HP, Digital Camera and DVD Movie Writer. Visit the site for details, topic ideas and to submit your abstract online.   News from a Seamless Partner MIPS New DSP Extension Enables Signal and Media Processing On the Industry-Standard MIPS® Architecture MIPS Technologies, Inc. announced the MIPS® DSP ASE, a new digital signal processing extension to the industry-standard MIPS architecture. The DSP ASE (application-specific extension) improves signal processing performance up to 300 percent over a range of embedded applications. Supported by a complete suite of software development tools, including Mentor's Seamless Hardware/Software Co-Verification Processor Support Package, and the MIPS DSP Library, the DSP ASE enables SoC designers to simplify their design environment and lower system cost by eliminating hardwired logic and migrating DSP functionality onto a MIPS-Based™ host processor. Find out more.   Co-Verification CD Request a CD that includes information on Seamless for hardware/software co-verification as well as a product demonstration.   Technical Publications Available Optimizing the Design and Verification of Embedded Systems Seamless Hardware/Software Co-Verification of FPGAs Managing Design Complexity through High-Level C-Model Verification Check out the entire archive of technical papers available.     Pass this newsletter on to a colleague! If this newsletter has been forwarded to you from a colleague and you would you like to continue to receive this monthly newsletter, register now. We will send you the latest technical publications, release information, and upcoming events. We would appreciate any feedback you have regarding this newsletter's content.   Return to Top   Best Regards, Mentor Graphics Corporation SoC Design and Verification Division http://www.mentor.com/soc/verification If you do not wish to receive future SoC Design and Co-Verification News updates, update your subscription (or reply to this email message with "Optout dolinsky@gsu.by" in the subject). Mentor Graphics 8005 SW Boeckman Road Wilsonville, OR, 97070, USA 800-547-3000 or 503-685-8000 Copyright© 2002 Mentor Graphics Corporation. Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. C-Bridge and Platform Express are trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.