Toshiba Rolls Out New Single-Chip High-Definition Digital Multimedia Decoder Chip
Device Functionality Supports Digital Satellite, Cable and Terrestrial Broadcasting Systems as Well as Emerging HD applications
SAN JOSE, Calif., April 21 /PRNewswire/ -- Toshiba America Electronic Components, Inc. (TAEC)* today announced a new single-chip high-definition (HD) digital multimedia decoder device with an integrated 64-bit 200 megahertz (MHz) MIPS-based reduced instruction set computer (RISC) TX49 central processing unit (CPU), an MPEG-2 decoder and peripherals. Target applications for the TC81240TBG include HD set-top boxes and HDTVs incorporating the receiver for satellite, cable and terrestrial digital broadcasts as well as many new applications requiring HD capabilities. Sample and volume production quantities of the device are currently available.
"As part of Toshiba Corporation's overall strategy for the digital consumer market, Toshiba engineers designed the TC81240TBG HD digital multimedia decoder to address system requirements for the digital consumer vertical market segment," said Farhad Mafie, vice president of the ASSP Business Unit at TAEC. "The highly-integrated, high-performance, peripheral component interconnect (PCI)-based single-chip device incorporates a 64-bit MIPS-based RISC processor, MPEG-2 HD video decoder, a 2D graphics processor, an audio digital signal processor (DSP), an NTSC/PAL/SECAM video encoder and a transport stream demultiplexing processor. This device complements other Toshiba products for the digital consumer market and positions Toshiba as the true system solution provider in the digital consumer segment."
Key features of the TC81240TBG are as follows:
* Integrated 200MHz 64-bit MIPS-based RISC TX49 CPU with 32K-bytes each
of instruction and data cache.
* 2-channel MPEG-2 (MP@HL) decoding; supports all Advanced Television
Systems Committee formats.
* Can decode four channels of standard-definition television.
* Uses unified memory architecture; the same memory chips can be used
for the CPU and multimedia functions.
* Supports multiple audio standards, including Advanced Audio Coding,
Dolby Digital, MPEG-1 layers 1, 2 and 3.
* Incorporates high-quality video capture and display functions.
* Contains a versatile scaler to output multiple pictures on the screen.
* Integrated NTSC/PAL/SECAM video encoder.
* Includes a secondary video encoder for VCR recording.
* Contains a bit block transfer engine and alpha blending for
high-quality on-screen displays.
* Supports worldwide conditional access systems, including DES, TDES,
DVB and Multi-2 descramblers.
* Integrated input/output, including universal serial bus (USB), PCI,
universal asynchronous receiver-transmitter, general-purpose
input/output, SmartCard and Inter-IC bus.
Digital broadcasting is the future of television and the adoption of digital TVs is expected to accelerate rapidly as a result of the Federal Communications Commission ruling that 36-inch or larger TVs have integrated tuners and MPEG decoders. Toshiba initially supported digital TV makers with a three-part chip set for the back-end system of digital receivers; these three ICs are now integrated in the TC81240TBG.
Along with a reduced parts count, Toshiba incorporated upgraded functions into the new device. Enhanced MPEG-2 decoding capability now allows simultaneous decoding of two HD channels, and the CPU operating frequency was increased from 32-bit 133MHz to 64-bit 200MHz. The device supports additional interfaces, including USB, and also features unified memory architecture.
Pricing and Availability
Samples and volume production quantities of the device are currently available. Current pricing is $35.00 each in 300,000-piece quantities. TAEC can also provide evaluation tools, including reference boards and driver software.
Technical Specification Summary
Part Number TC81240TBG
CPU TX49/H2 core with 200MHz operation and 32K-bytes
each of 4-way selectable data cache and
Decoder MPEG-2 video decoder (MP@HL)
Encoder NTSC/PAL/SECAM video encoder
Memory Interface Unified memory architecture
Supports DDR-type synchronous dynamic random
Other Built-in Circuits Descrambler (DES, TDES, DVB, Multi-2)
Transport stream demultiplexing processor
Direct memory access and peripheral controller
Package 648-ball tape ball grid array
Combining quality and flexibility with design engineering expertise, TAEC brings a breadth of advanced, next-generation technologies to its customers. This broad offering includes semiconductors, flash memory-based storage solutions, optical communication devices, displays and rechargeable batteries for the computing, wireless, networking, automotive and digital consumer markets.
TAEC is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba, the third largest semiconductor company worldwide in terms of global sales for the year 2002 according to Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a world leader in high-technology products with more than 300 major subsidiaries and affiliates worldwide. For additional company and product information, please visit TAEC's website at chips.toshiba.com. For technical inquiries, please e-mail Tech.Questions@taec.toshiba.com.
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Web site: http://www.chips.toshiba.com/