comp.dsp FAQ [2 of 4]

Archive-name: dsp-faq/part2
Last-modified: Wed September 30 1998

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                         Q2: ALGORITHMS AND STANDARDS
Q2.1: Where can I get public domain algorithms for general-purpose DSP?

   Updated 12/31/96
         The following archives contain things such as matrix
          operations, FFT's and generally useful things like that, as
          opposed to complete applications.
         Netlib serves some of this software via email. Try mail to
          netlib@ORNL.GOV with "send help" in the subject field.
   To Obtain:
          For Europe:
          X.400: s=netlib; o=nac; c=no;
          EUNET/uucp: nac!netlib
   For more information:
          See Jack J. Dongarra and Eric Grosse, "Distribution of
          Mathematical Software Via Electronic Mail," Comm. ACM (1987)
          A similar collection of statistical software is available from

          The symbolic algebra system REDUCE is supported by

    NSWC Library
          The Naval Surface Warfare Center has a library of mathematical
          Fortran subroutines that may be of use. The NSWC library is a
          library of general-purpose Fortran subroutines that provide a
          basic computational capability in a variety of mathematical
          activities. Emphasis has been placed on the transportability
          of the codes. Subroutines are available in the following
          areas: Elementary Operations, Geometry, Special Functions,
          Polynomials, Vectors, Matrices, Large Dense Systems of Linear
          Equations, Banded Matrices, Sparse Matrices, Eigenvalues and
          Eigenvectors, l1 Solution of Linear Equations, Least-Squares
          Solution of Linear Equations, Optimization, Transforms,
          Approximation of Functions, Curve Fitting, Surface Fitting,
          Manifold Fitting, Numerical Integration, Integral Equations,
          Ordinary Differential Equations, Partial Differential
   For more information:
          NSWC Library of Mathematical Subroutines
          Report No.: NSWC TR 90-21, January 1990
          by Alfred H. Morris, Jr.
          Naval Surface Warfare Center (E43)
          Dahlgren, VA 22448-5000
          [Witold Waldman,]
    IEEE Press book "Programs For Digital Signal Processing"
         You can get the Fortran source code from the IEEE Press book
          "Programs For Digital Signal Processing." See question 1.2.5.
Q2.2: What are CELP and LPC? Where can I get the source for CELP and LPC?

   Updated 9/24/98
         CELP stands for "code excited linear prediction". LPC stands
          for "linear predictive coding". They are compression
          algorithms used for low bit rate (2400 and 4800 bps) speech
          The U.S. DoD's Federal-Standard-1016 based 4800 bps code
          excited linear prediction voice coder version 3.2 (CELP 3.2)
          Fortran and C simulation source codes are available for
          worldwide distribution (on DOS diskettes, but configured to
          compile on Sun SPARC stations) from NTIS and DTIC. Example
          input and processed speech files are included. A Technical
          Information Bulletin (TIB), "Details to Assist in
          Implementation of Federal Standard 1016 CELP," and the
          official standard, "Federal Standard 1016, Telecommunications:
          Analog to Digital Conversion of Radio Voice by 4,800
          bit/second Code Excited Linear Prediction (CELP)," are also
   To obtain CELP:
          Available through the National Technical Information Service:
    U.S. Department of Commerce
    5285 Port Royal Road
    Springfield, VA 22161
    (800) 553-6847
          FS-1016 CELP 3.2 may also be obtained from
          .tar.Z or file://
          LPC is available from
          MATLAB software for LPC-10 is available from
 Also, postscript
          copies of tutorials of speech coding can be found at
   For more information:
     * The following articles describe the Federal-Standard-1016 4.8-kbps
       CELP coder (it's unnecessary to read more than one):
     Campbell, Joseph P. Jr., Thomas E. Tremain and Vanoy C. Welch, The
     Federal Standard 1016 4800 bps CELP Voice Coder, Digital Signal
     Processing, Academic Press, 1991, Vol. 1, No. 3, p. 145-155.
     Campbell, Joseph P. Jr., Thomas E. Tremain and Vanoy C. Welch, The
     DoD 4.8 kbps Standard (Proposed Federal Standard 1016), in Advances
     in Speech Coding, ed. Atal, Cuperman and Gersho, Kluwer Academic
     Publishers, 1991, Chapter 12, p. 121-133.
     Campbell, Joseph P. Jr., Thomas E. Tremain and Vanoy C. Welch, The
     Proposed Federal Standard 1016 4800 bps Voice Coder: CELP, Speech
     Technology Magazine, April/May 1990, p. 58-64.
       Additional information on CELP can also be found in the
       comp.speech FAQ.
     * The voicing classifier used in the enhanced LPC-10 (LPC-10e) is
       described in: Campbell, Joseph P., Jr. and T. E. Tremain,
       Voiced/Unvoiced Classification of Speech with Applications to
       the U.S. Government LPC-10E Algorithm, Proceedings of the IEEE
       International Conference on Acoustics, Speech, and Signal
       Processing, 1986, p. 473-6.
       The U. S. Federal Standard 1015 (NATO STANAG 4198) is described
       in: Thomas E. Tremain, The Government Standard Linear Predictive
       Coding Algorithm: LPC-10, Speech Technology Magazine, April 1982,
       pp. 40-49.
   [Most of the above from Joe Campbell,, with
   additions from Dan Frankowski,, and Ed Hall,] 
Q2.3: What is ADPCM? Where can I get source for it?

   Updated: 1/7/97
   ADPCM stands for Adaptive Differential Pulse Code Modulation. It is a
          family of speech compression and decompression algorithms. A
          common implementation takes 16-bit linear PCM samples samples
          and converts them to 4-bit samples, yielding a compression
          rate of 4:1.
   To obtain:
          There is public domain C code available via anonymous ftp at
          file:// written by Jack Jansen
          (email It is very programmer-friendly. The
          ADPCM code used is the Intel/DVI ADPCM code which is being
          recommended by the IMA Digital Audio Technical Working Group.
          It allows the following calls:

adpcm_coder(short inbuf[], char outbuf[], int nsample,
        struct adpcm_state *state);
adpcm_decoder(char inbuf[], short outbuf[], int nsample,
        struct adpcm_state *state);

          Note that this is NOT a G.722 coder. The ADPCM standard is much
          more complicated, probably resulting in better quality sound
          but also in much more computational overhead.
          The routines have been tested on numerous platforms, and will
          easily compress and decompress millions of samples per second
          on current hardware.
   For more information:
          The G.721/722/723 packages are available from ITU at

          This is also available as:
          [From Dan Frankowski,; Jack Jansen,
Q2.4: What is GSM? Where can I get source for it?

   Updated 1/7/96
         GSM is a standard for digital cellular telephony used in
          Europe. In this context, GSM also refers to the speech coder
          used in GSM telephones.
          The Communications and Operating Systems Research Group (KBS)
          at the Technische Universitaet Berlin is currently working on
          a set of UNIX-based tools for computer-mediated
          telecooperation that will be made freely available.
          As part of this effort we are publishing an implementation of
          the European GSM 06.10 provisional standard for full-rate
          speech transcoding, prI-ETS 300 036, which uses RPE/LTP
          (residual pulse excitation/long term prediction) coding at 13
          GSM 06.10 compresses frames of 160 13-bit samples (8 kHz
          sampling rate, i.e. a frame rate of 50 Hz) into 260 bits; for
          compatibility with typical UNIX applications, our
          implementation turns frames of 160 16-bit linear samples into
          33-byte frames (1650 Bytes/s). The quality of the algorithm is
          good enough for reliable speaker recognition; even music often
          survives transcoding in recognizable form (given the bandwidth
          limitations of 8 kHz sampling rate).
          The interfaces offered are a front end modeled after
          compress(1), and a library API. Compression and decompression
          run faster than realtime on most SPARCstations. The
          implementation has been verified against the ETSI standard
          test patterns.
          Jutta Degener, Carsten Bormann

          Communications and Operating Systems Research Group, TU Berlin
          Fax: +49.30.31425156, Phone: +49.30.31424315
   To obtain:

          ar.gz. An alternative site is
 Try also:

   [From Dan Frankowski,; Jutta Degener,]
Q2.5: How does pitch perception work, and how do I implement it on my DSP

   Updated 6/3/98
         Pitch is officially defined as "That attribute of auditory
          sensation in terms of which sounds may be ordered on a musical
          scale." Several good examples illustrating the subtleties of
          pitch perception are included in the "Auditory Demonstrations
          CD" which is available from the Acoustical Society of America,
          Woodbury, NY 10797 for $20.
          A good general reference about the psychology of pitch
          perception is the book:
     B.C.J. Moore, An Introduction to the Psychology of Hearing,
     Academic Press, London, 1997.
          This book is available in paperback and makes a good desk
          An algorithm implementation that matches a large body of
          psychoacoustical work, but which is computationally very
          intensive, is presented in the paper:
     Malcolm Slaney and Richard Lyon, "A Perceptual Pitch Detector,"
     Proceedings of the International Conference of Acoustics, Speech,
     and Signal Processing, 1990, Albuquerque, New Mexico. Available for
     ftp at
          The definitive papers describing the use of such a perceptual
          pitch detector as applied to the classical pitch literature is
     Ray Meddis and M. J. Hewitt. "Virtual pitch and phase sensitivity of
     a computer model of the auditory periphery. " Journal of the
     Acoustical Society of America 89 (6 1991): 2866-2682. and
          The current work that argues for a pure spectral method starts
          with the work of Goldstein:
     J. Goldstein, "An optimum processor theory for the central formation
     of the pitch of complex tones," Journal of the Acoustical Society of
     America 54, 1496-1516, 1973.
          Two approaches are worth considering if something approximating
          pitch is appropriate. The people at IRCAM have proposed a
          harmonic analysis approach that can be implemented on a DSP:
     Boris Doval and Xavier Rodet, "Estimation of Fundamental Frequency
     of Musical Sound Signals," Proceedings of the 1991 International
     Conference on Acoustics, Speech, and Signal Processing, Toronto,
     Volume 5, pp. 3657-3660.
          The classic paper for time domain (peak picking) pitch
          algorithms is:
     B. Gold and L. Rabiner, "Parallel processing techniques for
     estimating pitch periods of speech in the time domain," Journal of
     the Acoustical Society of America, 46, pp 441-448, 1969.
   Finally, a word of caution:
          Pitch is not single-valued. We can hear a sound and match it to
          several different pitches. Imagine the number of instruments in
          an orchestra, each with its own pitch. Even a single sound can
          have more than one pitch. See for example Demonstration 27 from
          the ASA Auditory Demonstrations CD.
   [The above from Malcolm Slaney, Interval Research, and John Lazzaro,
   U.C. Berkeley.]
          Another interesting piece of information on pitch perception
          can be found at
          [Stephan M. Sprenger,]
Q2.6: What standards exist for digital audio? What is AES/EBU? What is S/PDIF?

   Updates 1/8/97
         Try the ITU (International Telecommunication Union) homepage at

         The "AES/EBU" (Audio Engineering Society / European Broadcast
          Union) digital audio standard is probably the most popular
          digital audio standard today. Most consumer and professional
          digital audio devices (CD players, DAT decks, etc.) that
          feature digital audio I/O support AES/EBU.
          AES/EBU is a bit-serial communications protocol for
          transmitting digital audio data through a single transmission
          line. It provides two channels of audio data (up to 24 bits
          per sample), a method for communication control and status
          information ("channel status bits"), and some error detection
          capabilities. Clocking information (i.e., sample rate) is
          derived from the AES/EBU bit stream, and is thus controlled by
          the transmitter. The standard mandates use of 32 kHz, 44.1
          kHz, or 48 kHz sample rates, but some interfaces can be made
          to work at other sample rates.
          AES/EBU provides both "professional" and "consumer" modes. The
          big difference is in the format of the channel status bits
          mentioned above. The professional mode bits include
          alphanumeric channel origin and destination data, time of day
          codes, sample number codes, word length, and other goodies.
          The consumer mode bits have much less information, but do
          include information on copy protection (naturally).
          Additionally, the standard provides for "user data", which is
          a bit stream containing user-defined (i.e.,
          manufacturer-defined) data. According to Tim Channon, "CD user
          data is almost raq CD subcode; DAT is StartID and SkipID. In
          professional mode, there is an SDLC protocol or, if DAT, it
          may be the same as consumer mode."
          The physical connection media are commonly used with AES/EBU:
          balanced (differential), using two wires and shield in
          three-wire microphone cable with XLR connectors; unbalanced
          (single-ended), using audio coax cable with RCA jacks; and
          optical (via fiber optics).
         "S/P-DIF" (Sony/Philips Digital Interface Format) typically
          refers to AES/EBU operated in consumer mode over unbalanced
          RCA cable. Note that S/P-DIF and AES/EBU mean different things
          depending on how much of a purist you are in the digital audio
          world; see the Finger article below.
          Finger, Robert, AES3-199X: The Revised Two Channel Digital
          Audio Interface (DRAFT), presented at the 91st Convention of
          the Audio Engineering Society, October 4-8, 1991. Reprints:
          AES, 60 East 42nd St., New York, NY, 10165.
          [The above from Phil Lapsley and Tim Channon,
Q2.7: What is mu-law encoding? Where can I get source for it?

   Updated 1/7/97
         Mu-law (also "u-law") encoding is a form of logarithmic
          quantization or companding. It's based on the observation that
          many signals are statistically more likely to be near a low
          signal level than a high signal level. Therefore, it makes
          more sense to have more quantization points near a low level
          than a high level. In a typical mu-law system, linear samples
          of 14 to 16 bits are companded to 8 bits. Most telephone
          quality codecs (including the Sparcstation's audio codec) use
          mu-law encoded samples.
          Desktop Sparc machines come with routines to convert between
          linear and mu-law samples. On a desktop Sparc, see the man
          page for audio_ulaw2linear in /usr/demo/SOUND/man.
   To obtain:
          Craig Reese posted the source of similar routines to comp.dsp
          in August '92. These are archived on
          ITU-T (formerly CCITT) Recommendation G.711 (very difficult to
          Michael Villeret, et. al, A New Digital Technique for
          Implementation of Any Continuous PCM Companding Law, IEEE Int.
          Conf. on Communications, 1973, vol. 1, pp. 11.12-11.17.
          MIL-STD-188-113, Interoperability and Performance Standards for
          Analog-to-Digital Conversion Techniques, 17 February 1987.
          TI Digital Signal Processing Applications with the TMS320
          Family (TI literature number SPRA012A), pp. 169-198.
   [From Joe Campbell; Craig Reese,; Sepehr
   Mehrabanzad,; Keith Kendall,]
Q2.8: How can I do CD <-> DAT sample rate conversion?

   Updated 12/31/96
          CD players use a 44.1 kHz sample rate, whereas DAT uses a 48
          kHz sample rate. This means that you must do sample rate
          conversion before you can get data from a CD player directly
          into a DAT deck.
          [From Ed Hall,]
          For a start, look at Multirate Digital Signal Processing by
          Crochiere and Rabiner (see FAQ section 1.1).
          Almost any technique for producing good digital low-pass
          filters will be adaptable to sample-rate conversion. 44.1:48
          and vice-versa is pretty hairy, though, because the lowest
          whole-number ratio is 147:160. To do all that in one go would
          require a FIR with thousands of coefficients, of which only
          1/147th or 1/160th are used for each sample--the real problem
          is memory, not CPU for most DSP chips. You could chain several
          interpolators and decimators, as suggested by factoring the
          ratio into 3*7*7:2*2*2*2*2*5. This adds complexity, but
          reduces the number of coefficients required by a considerable
          [From Lou Scheffer:]
          Theory of operation: 44.1 and 48 are in the ratio 147/160. To
          convert from 44.1 to 48, for example, we (conceptually):
         1. interpolate 159 zeros between every input sample. This
            raises that data rate to 7.056 MHz. Since it is equivalent
            to reconstructing with delta functions, it also creates
            images of frequency f at 44.1-f, 44.1+f, 88.2-f, 88.2+f, ...
         2. We remove these with an FIR digital filter, leaving a signal
            containing only 0-20 KHz information, but still sampled at a
            rate of 7.056 MHz.
         3. We discard 146 of every 147 output samples. It does not hurt
            to do so since we have no content above 24 KHz. In practice,
            of course, we never compute the values of the samples we
            will throw out.
          So we need to design an FIR filter that is flat to 20 KHz, and
          down at least X db at 24 KHz. How big does X need to be? You
          might think about 100 db, since the max signal size is roughly
          +-32767, and the input quantization +- 1/2, so we know the
          input had a signal to broadband noise ratio of 98 db at most.
          However, the noise in the stopband (20KHz-3.5MHz) is all
          folded into the passband by the decimation in step 3, so we
          need another 22 db (that's 160 in db) to account for the noise
          folding. Thus 120 db rejection yields a broadband noise equal
          to the original quantizing noise. If you are a fanatic, you
          can shoot for 130 db to make the original quantizing errors
          dominate, and a 22.05 KHz cutoff to eliminate even ultrasonic
          aliasing. You will pay for your fanaticism with a penance of
          more taps, however.
   To obtain:
          There's a free implementation of Julius O. Smith III and
          someone else's "bandwidth-limited interpolation" rate
          conversion algorithm.
          The paper available as
          terpolation.eps.Z explains the algorithm. The source code in
, and
 implements the
          algorithm. It all works quite well.
          [From Kevin Bradley,]:
          I have an implementation of polyphase resampling for various
          rates in MATLAB and C at
          got comments, and people might find it useful.
          [From Fritz M. Rothacher,]:
          You can add my Ph.D. thesis on sample-rate conversion to the
          Fritz M. Rothacher, Sample-Rate Conversion: Algorithms and VLSI
          Implementation, Ph.D. thesis, Integrated Systems Lab, Swiss
          Federal Institute of Technology, ETH Zuerich, 1995, ISBN
          It can also be downloaded from my homepage at

Q2.9: Wavelets

   Updated 6/3/98 
         In short, wavelets are a way to analyze a signal using base
          functions which are localized both in time (as diracs, but
          unlike sine waves), and in frequency (as sine waves, but
          unlike diracs). They can be used for efficient numerical
          algorithms and many DSP or compression applications.
          The mathematical theory behind wavelets (and other related
          transforms) is given in the appendix of the XWPL reference
          manual. The XWPL manual can be found at

          Other sources of information on wavelets are:
          + a newsletter, "Wavelet Digest". Subscriptions for Wavelet
            Digest: E-mail to with "subscribe"
            as subject. The Wavelet Digest can also be found at
          + Dr. Amara Graps' Wavelet Library
         The best introduction to wavelet transforms is in:
     Wavelets and Signal Processing- Oliver Rioul and Martin Vetterli,
     IEEE Signal Processing magazine, Oct. 91, pp 14-38
          A good introductory book on wavelets:
     Randy K. Young, Wavelet Theory and Its Applications, Kluwer
     Academic Publishers, ISBN 0-7923-9271-X, 1993.
          A more thorough book:
     Ali N. Akansu and Richard A. Haddad, Multiresolution Signal
     Decomposition Transforms, Subbands, Wavelets Academic Press, Inc.,
     ISBN 0-12-047140-X
          A couple more interesting papers:
     Wavelets and Filter banks: Theory and Design, IEEE Transactions on
     Signal Processing, Vol. 40, No.9, Sept. 1992, pp 2207-2232
     Mac Cody's articles in Dr. Dobb's Journal, April 1992 and April
     Paper by Ingrid Daubechies in IEEE Trans. on Info. theory , vol 36.
     No.5 , Sept 1990 and a book titled " Ten lectures on Wavelets" deal
     with the mathematical aspects of the WT.
          Binaries are available for the following platforms: Sun
          Sparcstations running SunOS 4.1 or Solaris 2.3, NeXT machines
          running NeXTstep 3.0 or higher, with an X server, Silicon
          Graphics machines (IRIS), DEC Alpha AXP running OSF/1 1.2 or
          higher, i386/i486 PC compatible with Linux 0.99.
          There is also a sample data directory containing interesting
   More information:

          [From Fazal Majid]:
    Rice Wavelet Tools
          Announcing Release 2.0 of rice-wlet-tools. This is a collection
          of MATLAB of "mfiles" and "mex" files for twoband and M-band
          filter bank/wavelet analysis from the DSP group and
          Computational Mathematics Laboratory (CML) at Rice University,
          Houston, TX. This release includes application code for
          Synthetic Aperture Radar despeckling and for deblocking of JPEG
          decompressed Images.
          The programs have been tested on Sparcstations running SunOS
          4.1.n with MATLAB 4.1. However, the "mex" code is generic and
          should run on other platforms (you may have to tinker the
          Makefiles a little bit to make this work). There are several
          utility routines all of them callable from MATLAB. All the C
          files (leading to the mex files) can also be directly accessed
          from other C or Fortran code.
          A collection of of papers and tech. reports from the DSP group
          is also available. You could obtain this distribution of
          software and papers by anonymous ftp from
   To obtain:
          Anonymous FTP: ( in directories
          /pub/reports and /pub/software.
          Report problems/bugs and installation info on non-SUN/non-unix
          platforms send mail to (or

Q2.10: How do I calculate the coefficients for a Hilbert transformer?

   Updated 6/3/98
          For all the gorey details, I suggest the paper: Andrew Reilly
          and Gordon Frazer and Boualem Boashash: Analytic signal
          generation---tips and traps, IEEE Transactions on Signal
          Processing, no. 11, vol. 42, Nov. 1994, pp. 3241-3245.
          For comp.dsp, the gist is:
         1. Design a half-bandwidth real low-pass FIR filter using
            whatever optimal method you choose, with the principle
            design criterion being minimisation of the maximum
            attenuation in the band f_s/4 to f_s/2.
         2. Modulate this by exp(2 pi f_s/4 t), so that now your
            stop-band is the negative frequencies, the pass-band is the
            positive frequencies, and the roll-off at each end does not
            extend into the negative frequency band.
         3. either use it as a complex FIR filter, or a pair of I/Q real
            filters in whatever FIR implementation you have available.
          If your original filter design produced an impulse response
          with an even number of taps, then the filtering in 3 will
          introduce a spurious half-sample delay (resampling the real
          signal component), but that does not matter for many
          applications, and such filters have other features to
          recommend them.
          Andrew Reilly []
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Q3.1: What are the available DSP chips and chip architectures?

   Updated 9/24/98
         The "big four" programmable DSP chip manufacturers are Texas
          Instruments, with the TMS320 series of chips; Motorola, with
          the DSP56000, DSP56100, DSP56300, DSP56600, and DSP96000
          series; Lucent Technologies (formerly AT&T), with the DSP1600
          and DSP3200 series; and Analog Devices, with the ADSP2100 and
          ADSP21000 series. A good overview of programmable DSP chips is
          published periodically in EDN and Computer Design magazines.
          You may also want to check out Berkeley Design Technology's
          home page, which has a number of articles on choosing DSP
          processors, as well as a "Pocket Guide to DSP Processors and
          Cores" in downloadable PostScript. Brief overviews of various
          DSP processors, cores, and general-purpose processors can be
          found at
          Here's a less ambitious chip breakdown by manufacturer:
          10 to 50 MIPS 16-bit fixed point DSPs; 40-bit accumulator;
          24-bit instructions. Large number of family members with
          different configurations of on-chip memory and serial ports,
          timers, and host ports. ADSP-21mspxx members include an on-chip
          20/25/33 MHz floating-point DSP; Supports 32-bit fixed-point,
          IEEE format 32-bit floating-point, and 40-bit floating-point;
          40-bit registers plus an 80-bit accumulator that can be divided
          into two 32-bit registers and a 16-bit register.
   ADSP-2106x ("SHARC"):
          40 MIPS, 32-bit floating-point DSPs based on ADSP-21020. 32-bit
          address bus, 32-bit data bus; 1-4 Mbits on-chip memory; six
          communication ports, timer, two serial ports.
          Up to 120 MIPS 16-bit fixed-point DSPs. 16-bit address bus;
          36-bit accumulators. Serial ports, parallel port; timer, bit
          manipulation unit. Various memory configurations.
          100 MIPS 16-bit fixed-point DSP. 20-bit address bus; eight
          40-bit accumulators. Two multipliers and SIMD-like
          capabilities. Serial ports, parallel port; timer, bit
          manipulation unit. Various memory configurations.
   DSP32C, DSP32xx:
          32-bit floating point with 40-bits accumulator and 16/24-bit
          fixed point. The 32C has three 512 x 32-bit RAMs, while the
          3210 has two 1k x 32-bit RAMs and a 256x32-bit boot ROM. 32C:
          Serial and parallel I/O, 3210: Serial I/O, timer,
          DMA-controller. 3210 available at 50 and 66MHz. Note: DSP3210
          and DSP3207 are discontinued and no longer available.
          20.5/27/33/40 MHz 24-bit fixed point DSP. 24-bit data bus, 16
          bit address bus, 56 bit accumulators (2), host interface port,
          serial ports (2), general purpose I/O pins, timer.
          40, 50, or 60 MHz 16-bit fixed-point DSP; 16-bit data bus, 40
          bit accumulators (2), host interface port, serial ports (2),
          timer, Codec. 2K words program RAM, 2K words data RAM on chip.
          66/80/100 MHz 24-bit fixed-point DSP; 24-bit address bus;
          56-bit accumulators (2), timers, serial interface, host
          interface port. Various memory configurations. DSP56305
          includes filter-, Viterbi-, and cyclic-code coprocessors.
          60 MHz 16-bit fixed point DSP aimed at low-power applications;
          40-bit accumulators (2), timer, serial interface, host
          interface port.
          20 MIPS 16-bit fixed point DSP; 36-bit accumulators (2), three
          internal address buses (two 16-bit, one 19-bit) and one 16-bit
          external address bus; three 16-bit internal data buses, one
          16-bit external data bus; serial ports, timers.
          IEEE format floating point DSP; two complete 32-bit data and
          address buses. 1K words program RAM, 64 words bootstrap ROM, 1K
          words data RAM, 1K words data ROM, host interface ports (2).
          Available in 33 MHz or 40 MHz.
          Family of low cost fixed-point DSPs; 16 bit data, 32 bit
          registers; Various RAM and ROM configurations; 16 bit I/O bus,
          serial ports.
          50 MHz fixed-point DSPs; 16 bit data, 32 bit registers; 12.5
          MIPS @ 50 MHz. The family members have different RAM and ROM
          A cross between the TMS320C2x and the TMS320C5x families. Same
          data path as the 'C2x, but pipeline of 'C5x; 16-bit data,
          32-bit registers; 20/28/40 MIPS; serial ports. The TMS320C24x
          are aimed at motor control solutions.
          27/33/40 MHz floating point DSPs; 32-bit floating-point, 24-bit
          fixed-point data, 40-bit registers; DMA controller; serial
          ports; some support for multi-processor arrays. Various ROM and
          RAM configurations.
          40/50 MHz floating-point DSP; extensive parallel processing
          support through 6 buffered byte-wide 20 Mb/s links and 6
          channel DMA; cache.
          50-MIPS enhanced TMS320C25 (double throughput); low overhead
          looping; 10 Kwords SRAM on chip.
          Up to 100 MIPS 16-bit fixed-point DSPs with a large number of
          specialized instructions. Family members differ in
          configuration of on-chip ROM/RAM and serial ports, autobuffered
          serial ports, host ports, and time-division multiplexed ports.
          200 MHz 16-bit fixed-point DSP with VLIW (very large
          instruction word), load/store architecture; 32 32-bit
          registers; very deep pipeline; two multipliers, ALUs, and
          shifters; cache.
          167 MHz 32-bit and 64-bit IEEE-754 floating-point DSP with VLIW
          (very large instruction word), load/store architecture; 32
          32-bit registers; very deep pipeline; two multipliers, ALUs,
          and shifters; cache.
          Four (two on 'C82) 50 MHz 32-bit fixed-point processors
          combined with a RISC supervisory processor in a single
          multichip module. 'C80 includes a video controller.
Q3.2: What is the difference between a DSP and a microprocessor?

   Updated 9/24/98
         The essential difference between a DSP and a microprocessor is
          that a DSP processor has features designed to support
          high-performance, repetitive, numerically intensive tasks. In
          contrast, general-purpose processors or microcontrollers
          (GPPs/MCUs for short) are either not specialized for a
          specific kind of applications (in the case of general-purpose
          processors), or they are designed for control-oriented
          applications (in the case of microcontrollers). Features that
          accelerate performance in DSP applications include:
          + Single-cycle multiply-accumulate capability; some
            high-performance DSPs have two multipliers that enable two
            multiply-accumulate operations per instruction cycle
          + Specialized addressing modes, for example, pre- and
            post-modification of address pointers, circular addressing,
            and bit-reversed addressing
          + Most DSPs provide various configurations of on-chip memory
            and peripherals tailored for DSP applications. DSPs
            generally feature multiple-access memory architectures that
            enable DSPs to complete several accesses to memory in a
            single instruction cycle
          + Specialized execution control. Usually, DSP processors
            provide a loop instruction that allows tight loops to be
            repeated without spending any instruction cycles for
            updating and testing the loop counter or for jumping back to
            the top of the loop
          + DSP processors are known for their irregular instruction
            sets, which generally allow several operations to be encoded
            in a single instructon. For example, a processor that uses
            32-bit instructions may encode two additions, two
            multiplications, and four 16-bit data moves into a single
            instruction. In general, DSP processor instruction sets
            allow a data move to be performed in parallel with an
            arithmetic operation. GPPs/MCUs, in contrast, usually
            specify a single operation per instruction
          While the above differences traditionally distinguish DSPs
          from GPPs/MCUs, in practise it is not important what kind of
          processor you choose. What is really important is to choose
          the processor that is best suited for your application; if a
          GPP/MCU is better suited for your DSP application than a DSP
          processor, the processor of choice is the GPP/MCU. It is also
          worth noting that the difference between DSPs and GPPs/MCUs is
          fading: many GPPs/MCUs now include DSP features, and DSPs are
          increasingly adding microcontroller features. [Ole Wolf,
Q3.3: Software for Analog Devices DSPs

   Updated 1/8/97
          John Sture has developed an assembler for the Analog Devices
          ADSP-2105. The latest version can be obtained by sending email
          to The executable and manual will be
          returned in uuencoded format. Source code license is available
          for compilation on other systems. Requires Analog Devices'
          ld21.exe version 5.1 linker or equivalent for linking
          The number for the Analog Devices DSP BBS is (617) 461-4258
          (300, 1200, 2400, 9600, 14400 bps), 8N1.
          You can also find files on Analog Devices' web site, or at
          their FTP site at
          [Analog Devices DSP Applications,]
          Lots of Analog Devices, Inc. DSP software is available in their
          application books like Digital Signal Processing Applications
          Using the ADSP-2100 Family. These books are not free, but
          they're not expensive either. There are some major applications
          like modems, LPC, GSM codec, speech recognition, etc.
          [George Biner,]
Q3.4: Software for Lucent Technologies (Formerly AT&T) DSPs

         Lucent Technologies provides application libraries for their
          DSPs at
Q3.5: Software for Motorola DSPs

         Motorola provides free software development tools that may be
          downloaded from the Motorola Web site at

         A free assembler for the Motorola DSP56000 exists, thanks to
          Quinn Jensen, The current version is 1.2.
          It is also available at
         There are two separate compiler sources for the Motorola
          DSP56000. One is the port of gcc 1.40 done by Andrew Sterian
          ( and the other is a port of gcc 1.37.1
          done by Motorola and returned to the FSF. Andrew's port has
          bowed to Motorola's version. Both may be portable to gcc2.x.x
          with some effort required. Neither of these comes with an
          assembler, but you can get a free DSP56000 assembler elsewhere
          (see Q3.2.1 above). The Motorola gcc source is available for
          FTP from:

          From Andrew Sterian, "My DSP56K compiler,
          while not supported nor as well tested as Motorola's,
          implements fixed-point arithmetic rather than floating-point
          arithmetic. This may be suitable for some applications. The
          5615 compiler also implements fixed-point arithmetic. To the
          best of my knowledge, Motorola does not have a C compiler for
          the 5615 family, although alternatives may exist. As of this
          writing (January 1997) I have not worked woth Motorola DSPs or
          compiler software for nearly 5 years so questions regarding my
          compilers may well be met with "Ummm... I have no idea."
          Both compilers were posted to alt.sources so any Usenet site
          that archives this newsgroup will have a copy. I have also
          found the 5616 compiler at

         Motorola provides a software archive that is available via
          World-Wide Web from the software page at
 The archive includes
          macros for filters (FIR, IIR, adaptive) and floating-point
          functions. [Tim Baggett]
         Try FTP at ccrma-ftp.Stanford.EDU. The /pub/ directory contains
          free code for the Motorola DSP56001 and the NeXT platform.
         While the 68HC11 is not a DSP processor, emulators are
          available for those who might be interested in doing DSP on
          these processors:
          + New Mexico State University (NMSU) simulator engine,
   (Unix). Simulator
            engine with a command-line interface.
          + Sim6811,
            (Mac). Screen-oriented user interface based on the NMSU
            simulator engine (plus bug fixes).
          + EM11,
            (MS-DOS). Simulator and source-level debugger.
          + sim6811,
            (MS Windows 3.1/95). Simulator and source-level debugger.
          + Windows-Based Simulator,
            Windows 3.1/95/NT). Screen-oriented user interface, can
            interface emulator to external hardware.
Q3.6: Software for Texas Instruments DSPs

   Updated 9/24/98
         Spectron provides a downloadable program called WinConnex,
          which provides windows connectivity to the TI TMS320C31 DSK.
          It's available from Spectron's Web site at
 Look under the "products" menu.
   has some old, apparently public domain, assembler
          and related tools from TI for the TMS320 family. The directory
          is /pub/ham/dsp. [Antti-Pekka Virtanen,]
          For the TMS320C54x and TMS320C6x, try
          The TI DSP bulletin board is mirrored on, and on
 TI's world-wide web site is
 The TI site is the official one, but has
          no user contributed software. The file:
          file:// (might be
          broken) provides further guidance. Please restrict FTP session
          to outside of 8 am to 6 pm local time (10 pm to 8 am GMT).
          [Brad Hards,]
          { If anyone knows of any other sources for TI DSP software,
          please let us know at Thanks! } 
         Dr. Michael P. Hayes has written a GNU C-based compiler for the
          TMS320C30 and TMS320C40 families, available via anonymous FTP
          at The current version patches
          against gcc-2.7.2.
          [Dr. Michael P. Hayes,]
          Ted Rossin has written an assembler and linker for the
          TMS320C30. In his words, "It is somewhat limited by the fact
          that it can't handle expressions but it has worked fine for me
          over the past few years. There is no manual because it is a
          clone of the TI assembler and linker. However the linker
          command files use a different (easier to use) syntax. It runs
          on HP-UX workstations, Macs, IBM clones and believe it or not
          the Atari-ST (because I developed the code on it)."
          [Ted Rossin,]
          Dr. Michael P. Hayes has written a GNU-based assembler for the
          TMS320C30 and TMS320C40 families, available via anonymous FTP
          at The current version patches
          against binutils-2.7. According to Michael Hayes, the assembler
          syntax is compatible with the Texas Instruments TMS320C30
          assembler, although not all the Texas Instruments directives
          are supported. The binutils include a linker (ld), archiver
          (ar), disassembler (objdump), and other miscellaneous
          utilities. The object format of the assembler is compatible
          with the COFF format used by the Texas Instruments assembler.
          According to Michael Hayes, the binutils distribution can also
          be patched to support the GNU debugger, GDB. Included with the
          debugger is a simulator for the TMS320C30 and TMS320C40
          (written by Herman ten Brugge, The
          simulator allows cycle stepping, pipeline conflict analysis,
          code profiling, connection of memory or I/O to files, use of
          shared memory, automatic triggering of interrupts, etc.
          [Dr. Michael P. Hayes,]
          A freely distributable instruction set architecture simulator
          is available for the TMS320C30 DSP as part of the Web-Enabled
          Simulation framework from UT Austin at

          We have released all of the source code, as well as prebuilt
          C30 simulators for Windows '95/NT and Solaris 2.5
          The C30 simulator is bit-, cycle-, and instruction-accurate.
          The behavior of the C30 simulator has been validated against a
          C30 DSK board. The C30 simulator correctly reports interlocking
          and pipeline flushes, so it provides a convenient way to check
          C30 programs for these hidden delays. The C30 simulator is
          based on the C30 DSK tools by Keith Larson at Texas
          [Brian Evans,]
         Tick is a TMS320C40 parallel network detection and loader
          It is available from:
          Supports: Transtech, Hunt, and Traquair boards hosted by DOS,
          SunOS, Linux (a PC unix)
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