Metalanguage To Describe Processor System With Peripherals And External Environment

Ph.D. Dolinsky M., Ph.D. Ziselman I., Belotcky S.

High Level CAD in Electronics Department
System Programming Research Lab
Scaryna's Gomel State University, Belarus

This page propose metalanguage allowing to introduce and check descriptions of processors and their assemblers, with peripheral units and external environment. Essential developing of the metalanguage is made to support description of modern architecture
Introduction
Description of processor semantic
Description of assembler syntax
Semantic description metalanguage development
Simulation of system: processor & peripherals
Conclusion
Examples Index

Introduction

Developing of new microprocessor and microprocessor systems meet serious obstacles: volumes and difficulty of designed hardware and software systems is large, so traditional tools for creation the systems (including systems based on VHDL) became insuffic Functional possibilities of proposing tools consist from 3 groups: processor description, assembler program debugging and investigating designed hardware&software system. At first it is necessary to study (or to develop) described processor and to in

Description of processor semantic

We have introduced metalanguage to describe processor semantic and assembler syntax. Fundamental units of the meta-language are metacommands and metainstructions. Metacommands serves to describe processor storage elements such as registers, flags, memory Init(<name>,byte,<size_of_object_in_bytes>,<size_of_word_in_bytes>, <order_of_bytes>,<order_of_bits_in_byte>) [into <name2>(<address_in_name>)] and declaration of bit storage element (bit objects) is as follows: Init(<name>,bit,<size_of_object_in_bits>,<size_of_word_in_bits>, <order_of_bits>, [into <name2>(<address_in_name>)] Example 1. Registers bank declaration for Intel 8086. \1.0 Address: 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 22 24 DH DL AH AL BH BL CH CL BP SP SI DI CS SS DS ES IP DX AX BX CX \2.0 Init(R,byte,26,2,ordinal,ordinal) // registers bank declaration Keyword 'ordinal' means that high element is located in lower address.

Individual registers and flags (object variables) are described as fields of corresponding objects. For example, for integer variables one can use metacommand as follows:

Integer(<variable_name>,<object_name>,<address_in_object>,<variable_size>) Example 2. Declaration of registers AX, AH, AL for Intel 8086. Integer(AX,R,2,2) Integer(AH,R,2,1) Integer(AL,R,3,1) There are 2 special object types: MEMORY and FLAGS. Program variables, defined by corresponding assembler command (db, dw) automatically located in object MEMORY. Imbedded metaassembler flags (zero, carry, sign, ove After description objects and its variables it is necessary to describe processor instruction algorithms using metaassembler metainstructions. Metainstructions set is powerful and include arithmetical (integer, binary-decimal and float), logical, shift, move and branch metainstructions. So usually processor instruction described with one metainstruction, else one can use metafunction (sequence of few metainstructions) to describe needed processor instruction.

There are 7 formats of metainstructions:

Format 1. One-operand metainstructions

<metainstruction> <src_dst> <flags_field> metainstructions: _INC _DEC _CLR _PUSH Format 2. Two-operand metainstructions <metainstruction> <src> <dst> <flags_field> metainstructions: _MOV _MOVS _NOT _ACOS _ASIN _ATG _COS _FABS _FRAC _SIGN _SIN _TG _TRUNC Format 3. Three-operand metainstructions <metainstruction> <src1> <src2> <dst> <flags_field> metainstructions: _ADD _SUB _IMUL _MUL _FADD _FSUB _FMUL _AND _OR _XOR _SAR _SHL _SHR _EXP _LOG Format 4. Division metainstruction <metainstruction> <devidend> <divisor> <quotient> <remainder> <flags_field> metainstructions: _DIV _IDIV Format 5. Metainstruction _IF _IF <logical_operand> <metainstrucion or metafunction> <flags_field> Format 6. Metainstruction of unconditional branch _JUMP <label> <flags_field> Format 7. Metainstruction for flags setting _SET <dst> <logical_expression> Format 8. Zero-operand metainstructions <metainstruction> <flags_field> metainstructions: _EXIT _NOP _RETURN Processor instruction description may be done as shown below: function <instruction_name>(<operand_name_1>,... ..., <operand_name_n>): <default_operand_size> <metainstruction_1> (or <metafunction> or <instruction>) ... <metainstruction_k> (or <metafunction> or <instruction>) _return Example 3. Description of Intel 80x86 instruction CBW. { CBW - convert byte to word with sign extension from AL into AX, unchanging flags } function CBW _movs AL AX _return Example 4. Description of Intel 80x86 instruction IDIV. { IDIV source - if source-byte then AL := quotient of (AX / source) AH := remainder of (AX / source) else AX := quotient of (DX,AX / source) DX := remainder of (DX,AX / source) OF,CF - is set or cleared as appropriate AF,PF,SF,ZF - is in undetermined state } function IDIV(source):size _if (size=1) _jump ActByte // jump onto label ActByte if size=1 _idiv DX:4 source AX DX oc???? // dividing double word by word _exit // exit from metafunction ActByte. _idiv AX source AL AH oc???? // dividing word by byte _return There are three ways to set flags of described processor:

- by any metainstructions (_mov, for example):

_mov 1 CF - by special metainstruction _set: _set <flag_name> <logical_expression> - setting by embedded flags:

execution of each metainstruction form embedded flags; using of Flags_Field may change processor flags by values of embedded flags.

Description of assembler syntax

After processor semantic description it is necessary to define assembler. Full assembler description includes four formats of assembler commands: 1.<comment_line> 2.<constant_name> <equ-command> <constant_value> 3.[<memory_name>] <declaration_command> <data> 4.[<label>] [[<prefix>] <instruction> [<operands>]] [<comment_field>] In such a way there is proposed sequentially define the following information: symbol(s) of comment line, constant name format, assembler command for constants definition, memory name format, assembler command for memory definition, label format, symbol( Let we want to describe the following two group of instructions (Intel 80x86):

1) Instructions: INC, DEC, NEG, NOT

Format : <instruction> <operand> <operand> : <register> or <memory_with_size> Examples of assembler program fragments: ; Instruction Comment Operand Name ; inc ax ; Registers moRegister inc al ; increment moRegister inc nameB ; (nameB db ...) moNameRS1 inc nameB+4 ; Increment of byte aoN1_O inc nameB[bx] ; in memory aoN1_B inc nameW ; (nameW dw ...) moNameRS2 inc nameW+6 ; Increment of word aoN2_O inc nameW[bx] ; in memory aoN2_B inc byte ptr [bx] ; increment of byte aoMB inc word ptr [bx] ; increment of word aoMB inc word ptr 10[bx] ; with base register aoMW 2) Instructions: ROL, RCL, RCR, ROR, SAR, SAL, SHR, SHL Format : <instruction> <operand_1>,<operand_2> <operand_1> : <register> or <memory_with_size> <operand_2> : <register CL> or <number 1> Examples:

rol ax,cl ; circular shift left of register AX shr byte ptr [bx],1 ; logical shift right of byte ; register BX contains the byte address We need to use the following metacommands: Instruction Group <group_name> <number_of_operands> Instruction Set <instruction> ... <instruction> Group Combination <operand> ... <operand> Operand Set <name_of_set> = <operand> ... <operand> Operand Format <operand> <size> <syntax> <metaoperand> Part <name> = <identifier>...<identifier> Literal Standard <name> <number_system> <standard> <format> <sign> Names of metassembler standard operands,parts, and literals have the following prefixes: mc - MetaCharacter set mo - MetaOperand mp - MetaPart mr - Meta Range for literals There are recommended the following name prefixes for described processor elements: al - Assembler Literal ap - Assembler Part ao - Assembler Operand as - Assembler Set of operands Example 5. Fragment of assembler description. Instruction Group gID 1 Instruction Set INC DEC NEG NOT Group Combination moRegister asMemorySize Instruction Group gRS 2 Instruction Set ROL RCL RCR ROR SAR SAL SHR SHL Group Combination moRegister aoRS asMemorySize aoRS Operand Set asMemorySize = asMemory1 asMemory2 Operand Set asMemory1 = moNameRS1 aoN1_O Operand Set asMemory1 = aoN1_B aoMB Operand Set asMemory2 = moNameRS2 aoN2_O Operand Set asMemory2 = aoN2_B aoMW Operand F aoN1_O 1 <mpnamers1><alo> M(<alo>+@<mpnamers1>) F aoN1_B 1 <mpnamers1>[<aprb>] M(@<mpnamers1>+<aprb>) F aoMB 1 BYTE<mcs>PTR<mcs>[<aprb>] M(<aprb>) F aoMB 1 BYTE<mcs>PTR<mcs><aln>[<aprb>] M(<aln>+<aprb>) F aoN2_O 2 <mpnamers2><alo> M(<alo>+@<mpnamers2>) F aoN2_B 2 <mpnamers2>[<aprb>] M(@<mpnamers2>+<aprb>) F aoMW 2 WORD<mcs>PTR<mcs>[<aprb>] M(<aprb>) F aoMW 2 WORD<mcs>PTR<mcs><aln>[<aprb>] M(<aln>+<aprb>) Operand F aoRS 1 CL CL Operand F aoRS 1 1 1 Part apRB = BX BP Literal Standard alO 02 mrSigned2 <p>B 1 Literal Standard alO 10 mrSigned2 <p> 1 Literal Standard alO 10 mrSigned2 <p>D 1 Literal Standard alO 16 mrSigned2 <p>H 1 Literal Standard alN 02 mrUnion2 <p>B * Literal Standard alN 10 mrUnion2 <p> * Literal Standard alN 10 mrUnion2 <p>D * Literal Standard alN 16 mrUnion2 <p>H * where standard designations: moRegister - all regiaters moNameRS1,moNameRS2 - byte, word operands in memory <mcs> - &quot;blanks&quot; group mrSigned2 - integer in word (from 2 bytes) mrUnion2 - unsigned or integer in word @ - address user descriptions: aoN1_O , aoN2_O - byte, word operand in memory with offset aoN1_B , aoN2_B - byte, word operand in memory with base register aoMB , aoMW - byte, word operand in memory with offset and base register aoRS - register CL or number 1 M - name of object MEMORY

Semantic description metalanguage development

As defined above, introduced semantic description metalanguage includes metacommands to define processor memory element (registers, flags, stack, memory etc.) as well as metainstructions to describe processor instruction algorithms. The powerful set of m One can define metafunction called for concrete operand type by metacommand Operand Function, that has the following format: Operand Function <operand_name> <when_called> <metafunction_name> <operand_size> <operands_for_metafunction> where <when_called> - 'BEFORE' - if metafunction is called before execution of the instruction 'AFTER' - if metafunction is called before execution of the instruction To describe processor internal functional blocks we introduce special metacommand MarkFun, with that one can mark metafunctions executing at pointed time. Metacommand MarkFun has the following format: MarkFun <type_of_mark> <function_1> ... <function_n> where Type_of_Mark is as follows: Call - instruction of procedure call Ret - instruction of return from procedure Load - metafunction, doing once at loading of processor description Init - metafunction, doing every time before assembler program execution. It may be used to initialize processor memory elements Done - metafunction, doing every time after program execution is finished BeforeInstr - metafunction, doing before execution of every instruction of assembler program AfterInstr - metafunction, doing after execution of every instruction of assembler program For effective description of complex addressing mode metainstruction list was supplemented by the following metainstructions: _circ Reg Size Step Sign Dst // circular addressing _bitrev Reg Index Dst // bit-reversed addressing Examples of modern architecture features description for digital signal processor TMS320c40 with the metalanguage are given below.

Example 6. Fragment of description for processor TMS320c40. Description of bit-reversed and circular addressing.

Fragment of syntax description file:

; Operand with circular addressing Operand Format aoInd++% 4 *<apri>++(<aldisp>)% M(<apri>*4) Operand Format aoInd--% 4 *<apri>--(<aldisp>)% M(<apri>*4) Operand Format aoIndS++% 4 *<apri>++% M(<apri>*4) Operand Format aoIndS--% 4 *<apri>--% M(<apri>*4) Operand Format aoIndR++% 4 *<apri>++(<apir>)% M(<apri>*4) Operand Format aoIndR--% 4 *<apri>--(<apir>)% M(<apri>*4) Operand Format aoIndB++% 4 *<apri>++(<al01>)% M(<apri>*4) Operand Format aoIndB--% 4 *<apri>--(<al01>)% M(<apri>*4) ; Metafunction call for operand with circular addressing Operand Function aoInd++% After CalcCirc 4 <apri> <aldisp> 0 Operand Function aoInd--% After CalcCirc 4 <apri> <aldisp> -1 Operand Function aoIndS++% After CalcCirc 4 <apri> 1 0 Operand Function aoIndS--% After CalcCirc 4 <apri> 1 -1 Operand Function aoIndR++% After CalcCirc 4 <apri> <apir> 0 Operand Function aoIndR--% After CalcCirc 4 <apri> <apir> -1 Operand Function aoIndB++% After CalcCirc 4 <apri> <al01> 0 Operand Function aoIndB--% After CalcCirc 4 <apri> <al01> -1 ; Operand with bit-reversed addressing Operand Format aoIndB 4 *<apri>++(IR0)B M(<apri>*4) ; Metafunction call for operand with bit-reversed addressing Operand Function aoIndB After CalcBitR 4 <apri> IR0 Fragment of syntax description file: { CalcCirc (internal metafunction for circular addressing) ARn - address register step - step of changing sign - direction of changing } function CalcCirc(ARn,step,sign=0):4 _circ ARn 4 step sign ARn _return { CalcBitR (internal metafunction for bit-reversed addressing) ARn - address register AIR0 - index register } function CalcBitR(ARn,AIR0):4 _bitrev ARn AIR0 ARn _return Example 7. Fragment of description for processor TMS320c40. Instruction RPTS - repeat single instruction.

Fragment of semantic description file:

// Object and variable descriptions Init(Bank2 , byte, 20, 4, ordinal, invert) Integer ( ST, Bank2, 0, 4) // state register Init(F1,flags,32,1,ordinal) into Bank2(0) // flag register Integer(RM ,F1, 8,1) // flag &quot;repeat mode&quot; // Registers, used in repeat commands Init(Bank3 , byte, 12, 4, ordinal, invert) Integer ( RS, Bank3, 0, 4) // repeat start address Integer ( RE, Bank3, 4, 4) // repeat end address Integer ( RC, Bank3, 8, 4) // repeat counter // Auxiliary bits Init(tbit,bit,8,1,ordinal) Integer(sb,tbit,0,1) Integer(sh,tbit,1,1) { RPTS Repeat single instruction Syntax RPTS <src> Operation src -&gt; RC 1 -&gt; ST(RM) 1 -&gt; S Next PC -&gt; RS Next PC -&gt; RE Description The RPTS instruction allows a single instruction to be repeated a number of times without any penalty for looping. Fetches can also be made from the instruction register (IR), thus avoiding repeated memory access. The <src> operand is loaded into the repeat counter (RC). A 1 is written into the repeat mode bit of the status register ST (RM). A 1 is also written into repeat single bit (S). This indicate that the program fetches are to be performed only from the instruction register. The next PC is loaded into the repeat end address register (RE) and the repeat start address register (RS). For the immediate mode, <src> operand is assumed to be an unsigned integer and is not sign-extended. Status Bits Unaffected : LUF, LV, UF, N, Z, V, C Mode Bit OVM Operation is not affected by OVM bit value Example RPTS AR5 Before instruction: PC = 123h ST = 0h RE = 0h RS = 0h RC = 0h AR5 = 0FFh After instruction: PC = 124h ST = 100h RE = 124h RS = 124h RC = 0FFh AR5 = 0FFh } function RPTS(src):4 _movs PC RS // load repeat start address _movs PC RE // load repeat end address _movs 1 RM // set repeat mode bit of status register _movs 1 S // set repeat single bit _movs src RC // load repeat counter _movs 1 sb // set mode 'first execution of RPTS' _return // Metafunction executing after each instruction function AfterInstr:4 ... _if ((RM=1)&amp;(sb=1)) _jump BRep // First execution RPTS _if (RM=1) _jump DoRep // next instruction repeat ... _jump cont DoRep. _if (S=1) _jump RepS ... RepS. _if (RC&gt;0) _jump Next // repeat is not finished // ResetB. _mov 0 RM // reset repeat mode bit _mov 0 S // reset repeat single bit _movs RE+1 PC // set PC Next. _sub RC 1 RC // decrement repeat counter _if (RM=1) _movs RS PC // if repeat mode bit is 1 // set PC on repeat start _jump cont BRep. _mov 0 sb // reset mode 'first execution // of RPTS' cont. _nop _return // Initialization before start of assembler program function Start _movs 0 DP // Data Page Pointer _movs 8000 SP _movs 0 ST // -&gt; RM:=0 _movs 0 sb ... _return Fragment of syntax description file: ; Mark of initialization metafunction MarkFun Init Start ; Mark of metafunction that will been executed after each ; instruction execution MarkFun AfterInstr AfterInstr Example 8. Fragment of description for processor TMS320c40. Instruction RPTB - repeat block of instruction.

Fragment of semantic description file:

{ RPTB Repeat block of instructions Syntax RPTB <src> Operation src -&gt; RE 1 -&gt; ST(RM) Next PC -&gt; RS Description RPTB allows a block of instructions to be repeated a number of times without any penalty for looping. This instruction activates the block repeat mode of updating the PC. The <src> operand is a 24-bit unsigned immediate value that is loaded into the repeat end address (RE) register. A 1 is written into the repeat mode bit (RM) of status register ST to indicate that the PC is being updated in the repeat mode. The address of the next instruction is loaded into the repeat start address (RS) register. Status Bits Unaffected : LUF, LV, UF, N, Z, V, C Mode Bit OVM Operation is not affected by OVM bit value Example RPTB 127h Before instruction: PC = 123h ST = 0h RE = 0h RS = 0h After instruction: PC = 124h ST = 100h RE = 127h RS = 124h } function RPTB(src):4 _movs PC RS // load repeat start address _movs src RE // load repeat end address _movs 1 RM // set repeat mode bit of status register _movs 0 S // reset repeat single bit _movs 1 sb // set mode 'first execution of RPTS' _return // Metafunction executing after each instruction (see also above) function AfterInstr:4 ... _if ((RM=1)&amp;(sb=1)) _jump BRep _if (RM=1) _jump DoRep ... _jump cont DoRep. _if (S=1) _jump RepS _if (PC&lt;&gt;RE+1) _jump cont // blok is not ended _if (RC&gt;0) _jump Next _jump ResetB RepS. ... ResetB. _mov 0 RM _mov 0 S _movs RE+1 PC Next. _sub RC 1 RC _if (RM=1) _movs RS PC _jump cont BRep. _mov 0 sb _jump cont cont. _nop _return Example 9. Fragment of description for processor TMS320c40. Instructions BcondD - delayed branches.

Fragment of semantic description file:

// Auxiliary objects and variables Init(Bytes,byte,20,5,ordinal,ordinal) Integer(JMPa,Bytes,00,5) // branch address Integer(JMPS,Bytes,05,1) // execution address // Auxiliary metafunction for delayed branches function SetD(src):4 _mov 1 sh // set delayed brunch bit _movz src JUMPa // set branch address _movz PC+3 JUMPs // set execution address _return { BcondD Branch Conditionally (Delayed) Syntax BcondD <src> Operation If cond is true if <src> is in register addressing mode (Rn) <src> -&gt; PC if <src> is in PC-relative mode (label or address) displacement + PC +3 -&gt; PC else continue Description BcondD signifies a delayed branch that allows the three instructions after the delayed brunch to be fetched before the PC is modified. The effect is a single cycle branch and the three instructions following BcondD will not affect the cond. Status Bits Unaffected : LUF, LV, UF, N, Z, V, C Mode Bit OVM Operation is not affected by OVM bit value Example * * y:=(x-3.0)*1.5, if x<0 * y:="(x-3.0)-2.0," if x>=0 * LDF *+AR1(5),R2 ; Load X into R2 BGED SKIP ; if x&gt;=0 (delayed) goto SKIP ; delayed executions (executed with any x) LDF R2,R1 ; R1:=R2 SUBF 3.0,R1 ; R1:=R1 - 3.0 NOP ; third delayed instruction (empty) * MPYF 1.5,R1 ; Continue if loaded into R2 x<0 . . . SKIP SUBF 2.0,R1 ; Continue if loaded into R2 x>=0 } function BUD(oper):4 // unconditional delayed brunch SetD oper _return function BGED(oper):4 // delayed brunch on N=0 _if (N=0) SetD oper _return // Metafunction executing after each instruction function AfterInstr:4 ... _if ((sh=1)&amp;(JUMPs=PC)) _jump DoJUMP ... DoJUMP. _clr sh // reset delayed brunch bit _mov JUMPa PC // load branch address into PC _exit ... _return And finally full text of metafunction AfterInstr function AfterInstr:4 _if ((RM=1)&amp;(sh=1)) _jump JMP4D // RPTBD _if ((RM=1)&amp;(sb=1)) _jump BRep _if (RM=1) _jump DoRep _if (sh=1) _jump JMP4 _jump cont JMP4. _add 1 noJMP noJMP _if (noJMP=4) _mov 0 sh _if (noJMP=4) _movs addrJMP PC _jump cont JMP4D. _add 1 noJMP noJMP _if (noJMP=4) _mov 0 sh _if (noJMP=4) _jump DoRep _jump cont DoRep. _if (S=1) _jump RepS _if (PC&lt;&gt;RE+1) _jump cont // RPTB _if (RC&gt;0) _jump Next _jump ResetB RepS. _if (RC&gt;0) _jump Next // RPTS ResetB. _mov 0 RM _mov 0 S _movs RE+1 PC Next. _sub RC 1 RC _if (RM=1) _movs RS PC _jump cont BRep. _mov 0 sb _jump cont cont. _nop _return Example 10. Fragment of description for processor TMS320c40. Parallel instructions ABSF||STF

Fragment of syntax description file:

; ABSF src2,dst1 || STF src3,dst2 ; Declaration of instruction group with 3 operands: ; src2, dst1 || STF src3 and dst2 Instruction Group agABSF|| 3 Instruction Set ABSF NEGF Instruction Set TOIEEE FRIEEE Group Combination agABSF|| asIndirect1 ao||ABSF asIndirect1 ; Description of second operand ( dst1 || STF src3 ) Operand F ao||ABSF <n> <aidst1><mcs>||<mcs>STF<mcs><aisrc3> <aidst1> 1 <aisrc3> Fragment of semantic description file: function ABSF(src2,(dst1=src2,no=0,src3=0),dst2=0):4 // (no=1) ABSF src2,dst1 STF src3,dst2 _if (no=1) _fmov src3 tempF // store src3 into tempF _if (src2=0x7F80000000) _jump Ovflw _fabs src2 dst1 _fcom dst1 0.0 -0z00 _jump cont Ovflw. _mov 0x7FFFFFFFFF dst1 -10001 Cont. _if (no=1) _fmov tempF dst2 // execute STF src3,dst2 _return Examples 6-10 illustrate possibilities to describe processors with any complexity using the introduced metalanguage. Moreover, this metalanguage allows to describe not only processor but also peripherals and environment interacting with it.

Probabilistic commands for value setting

Probabilistic commands for value setting are using for random process simulating (call for interruptions etc.)

- Single probabilistic value setting

$Sp[Number] <expression>[:=<value>]... where Number is in interval 1..65535.
Value(s) setting by this command will be doing with probability 1/Number.

- Global probabilistic value setting

$SGp[Number] <expression>[:=<value>]... where Number is in interval 1..65535.
After this shadow command will be processed, each processor instruction execution call probabilistic value setting described by the shadow command. "Hot" start don't delete action of the shadow command.

- Global interval value setting

$SGi[Number] <expression>[:=<value>]... where Number is in interval 1..65535.
After this shadow command will be processed, execution of Number processor cycles call probabilistic value setting described by the shadow command. "Hot" start don't delete action of the shadow command.

- Cancel all global setting

$SGd All global settings (probabilistic as well interval) are cancelled.

Example 11. Processor Intel 8051. Global call for interruption with probability 0.01.

nop ;$SGp100 ie0:=1

Simulation of system: processor & peripherals

To describe peripherals we propose to use the same metalanguage as for processor description. This possibility is illustrated by doing of example from "TMS370 Microcontrollers. Application Report. (Texas Instrument Inc., 1994)": Vacuum Fluorescent Display Driver. In this example a microcontroller TMS370C010 interacts with a v We describe microcontroller TMS370C010, interruptions with timer, Serial Peripheral Interface module and 4 digit display common anode. Then the program given in application report were realized.

Conclusion

Described above metalanguage is powerful means for description of processor with peripherals and external environment. This fact is confirmed also by the list of already described processors:

  1. Digital signal processors from Texas Instruments TMS320c30, c40, c50, c80 (Master Processor) and from Analog Devices ADSP-210x0
  2. Transputers T414, T800
  3. Popular 8-bit microcontrollers and microprocessors Intel 8051, PICxxx, TMS370xxx, Intel 8080, Z80
  4. Popular 16-bit microprocessors: Intel 8086/8087, Intel 8096
  5. "Old" processors: PDP-11, IBM 360/370, Apple (6502)
  6. Diverse hypothetical processors (to research power of a metalanguage for processor description)
  7. Programmable microcalculators MC-61, MC-64
Moreover, the metalanguage is supported be comprehensive IDE (integrated development environment). IDE has standard multi-window interface (menu, window resizing & moving, mouse support, context-sensitive help, colour tuning, service etc) and standar The tool system works on IBM-compatible PC under management MS DOS or Windows (session DOS), has the versions under real and protected modes. The maximum configuration requires about 5 Mb on a hard disk and depends on a number of processor descriptions.

Examples Index

Example 1. Registers bank declaration for Intel 8086
Example 2. Declaration of registers AX, AH, AL for Intel 8086
Example 3. Description of Intel 80x86 instruction CBW
Example 4. Description of Intel 80x86 instruction IDIV
Example 5. Fragment of assembler description
Example 6. TMS320c40. Description of bit-reversed and circular addressing
Example 7. TMS320c40. Instruction RPTS - repeat single instruction
Example 8. TMS320c40. Instruction RPTB - repeat block of instruction
Example 9. TMS320c40. Instructions BcondD - delayed branches
Example 10. TMS320c40. Parallel instructions ABSF||STF
Example 11. Intel 8051. Global call for interruption with probability 0.01